Clear Ncore CCU snoop filter. There is hardware bug in NCORE CCU IP
and it is causing an issue in the coherent directory tracking of
outstanding cache lines.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I9ee67c94e6379d318516ae8f660a62323ce8d563
Explains that the SPMC_OPTEE build option is used to load the SPMC at
S-EL1 using an OP-TEE specific mechanism.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I71757d2d9ac98caf0ac6d8e64b221adaa0f70846
SCR_EL3.EA is set to 1 in BL31 initialization and is cleared before
entering to lower ELs(except for RAS FFH case "HANDLE_EA_EL3_FIRST_NS").
The cleared value persist even during run time when execution comes
back to EL3.
When SCR_EL3.EA is 0 and execution state is EL3, Async EAs(delivered
as SErrors) are implicitly masked and hence any Async EA by EL3 will
remain pending and will trap at the exception level EA is targeted
to and unmasked when entering lower EL.
This causes unexpected EA at lower EL. This is a very rare
to get SError in EL3 until unless there is any programming error.
This patch sets SCR_EL3.EA to 1 when entering EL3 from lower EL.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibb593369edb034f670fd85ee79adc9829b900a83
scr_el3 registers cannot be modified in lower ELs which means it retains
the same value which is stored in the EL3 cpu context structure for the
given world. So, we should not save the register when entering to EL3
from lower EL as we have the copy of it present in cpu context.
During EL3 execution SCR_EL3 value can be modifed for following cases
1. Changes which is required for EL3 execution, this change is temp
and do not need to be saved.
2. Changes which affects lower EL execution, these changes need to be
written to cpu context as well and will be retrieved when scr_el3
is restored as part of exiting EL3
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I9cc984ddf50e27d09e361bd83b1b3c9f068cf2fd
* changes:
feat(imx8mq): add BL31 PIE support
refactor(imx8mq): introduce BL31_SIZE
refactor(imx8mq): make use of setup_page_tables()
feat(imx8mq): always set up console
feat(imx8mq): remove empty bl31_plat_runtime_setup
feat(imx8mq): make IMX_BOOT_UART_BASE configurable via build parameter
Enable PIE support so the BL31 firmware can be loaded from anywhere
within the OCRAM (SRAM). For the PIE support we only need to replace
the BL31_BASE define by the BL31_START symbol which is a relocatable
and we need to enable it by setting ENABLE_PIE := 1.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Change-Id: Ie6a13e4ae0fdc6627a94798d7a86df7d5b310896
No functional change.
Introduce BL31_SIZE define and calculate the limits based on the
BL31_BASE and the BL31_SIZE define. Also make use of SZ_64K to make
it easier to read. This is required for later BL31 PIE support since
it drops the calculation based on the BL31_LIMIT and BL31_BASE.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Change-Id: I517074b866b5bf11841b51777f87c926b304488d
Improve code readability and align with other i.MX8M* platforms.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Change-Id: Ifd29b74872e3a567288d208de4827403078164e9
This aligns the i.MX8MQ platform behaviour with the other i.MX8M*
platforms by always setting up the console UART.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Change-Id: I1279d9cb4feb6e789422b9844cab711b8daae74e
Having this empty definition is actively harmful, as it prevents the
default weak function to be used, which does a switch of the console
state.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Change-Id: I3b78e0c524c4907714036dba573a44d8f9c48b09
This aligns the i.MX8MQ build with the other i.MX8M platforms by
allowing to override the default IMX_BOOT_UART_BASE value via a make
parameter.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Change-Id: Iad9b844517209fc7d051c61767f71ac9fa2b55c7
The functions stm32_pka_get_platdata() and stm32_saes_get_platdata()
are not used. They can be removed as we always use DT to retrieve
the device configuration.
This issue was triggered by sparse tool or when enabling warning
-Wmissing-prototypes.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I5cce9a0765144d694e8ddece37361ccbb85d1734
The issue is triggered when enabling -Wmissing-prototypes warning:
plat/st/common/stm32mp_crypto_lib.c:81:5: warning:
no previous prototype for 'get_plain_pk_from_asn1'
[-Wmissing-prototypes]
81 | int get_plain_pk_from_asn1(void *pk_ptr, unsigned int pk_len,
| ^~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ia36bbaba6e187ab47c203ddf0d7d017b210545cf
This includes the functions definitions, and avoids sparse warnings:
plat/st/stm32mp1/plat_image_load.c:13:6: warning:
symbol 'plat_flush_next_bl_params' was not declared.
Should it be static?
plat/st/stm32mp1/plat_image_load.c:21:16: warning:
symbol 'plat_get_bl_image_load_info' was not declared.
Should it be static?
plat/st/stm32mp1/plat_image_load.c:29:13: warning:
symbol 'plat_get_next_bl_params' was not declared.
Should it be static?
The issue was also found when enabling -Wmissing-prototypes warning:
plat/st/stm32mp1/plat_image_load.c:13:6: error:
no previous prototype for 'plat_flush_next_bl_params'
[-Werror=missing-prototypes]
13 | void plat_flush_next_bl_params(void)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
plat/st/stm32mp1/plat_image_load.c:21:17: error:
no previous prototype for 'plat_get_bl_image_load_info'
[-Werror=missing-prototypes]
21 | bl_load_info_t *plat_get_bl_image_load_info(void)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
plat/st/stm32mp1/plat_image_load.c:29:14: error:
no previous prototype for 'plat_get_next_bl_params'
[-Werror=missing-prototypes]
29 | bl_params_t *plat_get_next_bl_params(void)
| ^~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I0bb3052f6efd888462eab2fd8f18862e7fbf02b9
This issue was triggered by sparse tool:
plat/st/common/stm32mp_fconf_io.c:31:17: warning:
symbol 'metadata_block_spec' was not declared. Should it be static?
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I283d15792ed0e7ac5181e18aaf54010a0e61b370
with reference to feature 04c730 (feat(cpus): make cache ops conditional),
booting with caches in debug recovery means SCTLR_C_BIT will be 0.
Wrap the assert for the d-cache enabled check in CONDITIONAL_CMO and
plat_can_cmo calls to allow booting with d-cache disabled.
Signed-off-by: Channagoud kadabi <kadabi@google.com>
Change-Id: I80153df493d1ec9e5e354c7c2e6a14322d22c446
If compiling with STM32MP13 with DECRYPTION_SUPPORT != none, there is
a compilation error:
plat/st/common/stm32mp_crypto_lib.c:
In function 'plat_get_enc_key_info':
plat/st/common/stm32mp_crypto_lib.c:532:25:
error: implicit declaration of function 'zeromem'
[-Werror=implicit-function-declaration]
532 | zeromem(key, *key_len);
| ^~~~~~~
Adding #include <lib/utils.h> solves the error.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I0a20c5632f0379612149333e69875369d4cfca15
When -Wextra was added, the warning levels changed their meaning. Add a
description in the build option section and leave the security hardening
section as mostly a pointer to it.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iabf2f598d0bf3e865c9b991c5d44d2acb9572bd5
There is no reason to use macros from trusty spd header and creating
dependency on it. Use directly macros from lib/smccc.h
Co-developed-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I7cf1f76a5358ffc297c914f41c437469f5a42411
Updating documentation to reflect the new ARM_ROTPK_LOCATION variant of
the full ROTPK, as opposed to the hash of it.
Change-Id: I0f83c519bd607ef1270c7d30ee9bc55451ce4ae2
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Add support for ARM_ROTPK_LOCATION=devel_full_dev_rsa_key, which
implements the scenario where the platform provides the full ROTPK, as
opposed to the hash of it. This returns a 2kB development RSA key
embedded into the firmware.
The motivation for this patch is to extend our test coverage in the CI.
Right now, the authentication framework allows platforms to return
either the full ROTPK or a hash of it (*). However, the FVP platform
only supports returning a hash currently so we cannot easily exercise
the full key scenario. This patch adds that capability.
(*) Or even no key at all if it's not deployed on the platform yet, as
is typically the case on pre-production/developement platforms.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ie869cca1082410e63894e2b7dea2d31155684105
* changes:
fix(st-clock): avoid arithmetics on pointers
fix(st-clock): give the size for parent_mp13 and dividers_mp13 tables
fix(st-clock): remove useless switch
fix(st-clock): use Boolean type for tests
fix(st-regulator): use Boolean type for tests
fix(st-regulator): enclose macro parameters in parentheses
fix(st-regulator): rework for_each_*rdev macros
fix(st-regulator): explicitly check operators precedence
fix(st-pmic): define pmic_regs table size
fix(st-pmic): enclose macro parameter in parentheses
* changes:
fix(stm32mp1): rework DWL buffer cache invalidation
fix(stm32mp1): add const for strings in stm32mp_get_soc_name()
fix(st): use Boolean type for tests
fix(st): rework secure-status check in fdt_get_status()
fix(st): use indices when counting GPIOs in DT
fix(st): add U suffix for unsigned numbers
fix(st): explicitly check operators precedence
This patch fixes compilation error for gpt_init_l0_tables()
function in lib/gpt_rme/gpt_rme.c reported by GCC 13.0.0:
"gpt_rme/gpt_rme.c:765:5: error: conflicting types for
'gpt_init_l0_tables' due to enum/integer mismatch;
have 'int(unsigned int, uintptr_t, size_t)'
{aka 'int(unsigned int, long unsigned int, long unsigned int)'}"
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I38f28be290337e7d37d59b52cad7bde5b96b8d51
Introduce additional defines needed when compiling the QEMU platform
with SPMC at EL3.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: If6dbe41fa8761637e39579a1f6818dabc769c139
Prior to this commit a logical platform specific partition is added when
compiling with SPMC at EL3. Not all platform need to add a logical
platform so make this optional.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I3bdd2a91350330c1637e8d84765974bfb6b225d7
Supports S-EL2 SPMC + S-EL1 SP on qemu. S-EL1 SPs packaged in .pkg files
are added to the FIP as blob with an UUID. BL2 parses TB_FW_CONFIG to
know which SP blobs to load into memory.
Co-developed-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I4b61c4c048f31540d4f1ef9e05f0b12deb341e06
Updates the ABI between SPMD and the SPMC at S-EL1 so that the hard
coded SPMC manifest can be replaced by a proper manifest via TOS FW
Config. TOS FW Config is provided via QEMU_TOS_FW_CONFIG_DTS as a DTS
file when building. The DTS is turned into a DTB which is added to the
FIP.
Note that this is an incompatible change and requires corresponding
change in OP-TEE ("core: sel1 spmc: boot abi update").
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: Ibabe78ef50a24f775492854ce5ac54e4d471e369
Change function prototype of plat_css_get_scmi_info() to fix the GCC
sign conversion error "comparison between signed and unsigned integer
expressions". Changing channel_id type to unsigned int since it can
never be a negative value.
Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I579b21497329db40897c10d86c8fc68e4877f3db
Change variable type in function bl31_platform_setup() to fix the GCC
sign conversion error "comparison between signed and unsigned integer
expressions".
Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: Iff914bd7ad521883723c8fb34dd893412cce7fc5
Ensure that there is sufficient space in the memory
descriptor to accommodate the size of the composite memory
struct as part of the descriptor.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Iea646b144c59a2a1a171298cabb5f31040a8af31
Cortex-X2 erratum 2768515 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ib02688f7b6dc7f6ec305e68e8895174f6fd577a0
Cortex-A710 erratum 2768515 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If17fe04d3fda0dba6b8aabdd837a1c53e1830ed5
This patch also:
* Enforces the check of RES0 fields on EL3-RMM boot interface
and manifest
* Fixes a couple of nits on the EL3-RMM Boot Interface
documentation.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Idb9e38f9fcda2ba0655646a1e2c4fdbabd5cdc40
This corrects MISRA C2012-10.6:
The value of a composite expression shall not be assigned to an object
with wider essential type.
While at it change all the shift values to unsigned.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Idf9915313af965db2106095df7cb48a84f50c519
Fix MISRA C2012-10.3:
The value of an expression shall not be assigned to an object with
a narrower essential type or of a different essential type category.
Check buffer size is less than 4GB before casting the command argument.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iac1afcfe905c99b22cb39dc4104d351b0e647e5d
As the default part do nothing, all the code managing DWL buffer cache
invalidation can be under programmer flags.
This avoids running unneeded code if the flags are not enabled, and
corrects MISRA C2012-16.6:
Every switch statement shall have at least two switch-clauses.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I90d2951f9518509b3380295fb1a6ad6b9c5e551e
Jit Loon Lim
Madhukar Pappireddy
Jens Wiklander
Manish Pandey
Olivier Deprez
Lucas Stach
Yann Gautier
Lauren Wehrmeister
Channagoud kadabi
Boyan Karatotev
Joanna Farley
Akshay Belsare
AlexeiFedorov
Manish V Badarkhe
Sandrine Bailleux
Tamas Ban
Tony K Nadackal
Shruti Gupta
Marc Bonnici
Bipin Ravi
Javier Almansa Sobrino