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240 lines
5.1 KiB
240 lines
5.1 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &usart1;
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serial1 = &usart2;
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serial2 = &usart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &usart6;
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serial6 = &uart7;
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serial7 = &uart8;
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_csi: clk-csi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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};
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clk_i2s_ckin: i2s_ckin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_dsi_phy: ck_dsi_phy {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clk_usbo_48m: ck_usbo_48m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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usart2: serial@4000e000 {
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compatible = "st,stm32h7-usart";
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reg = <0x4000e000 0x400>;
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clocks = <&rcc USART2_K>;
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status = "disabled";
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};
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usart3: serial@4000f000 {
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compatible = "st,stm32h7-usart";
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reg = <0x4000f000 0x400>;
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clocks = <&rcc USART3_K>;
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status = "disabled";
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};
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uart4: serial@40010000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40010000 0x400>;
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clocks = <&rcc UART4_K>;
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status = "disabled";
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};
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uart5: serial@40011000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40011000 0x400>;
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clocks = <&rcc UART5_K>;
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status = "disabled";
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};
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uart7: serial@40018000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40018000 0x400>;
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clocks = <&rcc UART7_K>;
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status = "disabled";
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};
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uart8: serial@40019000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40019000 0x400>;
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clocks = <&rcc UART8_K>;
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status = "disabled";
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};
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usart6: serial@44003000 {
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compatible = "st,stm32h7-usart";
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reg = <0x44003000 0x400>;
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clocks = <&rcc USART6_K>;
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status = "disabled";
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};
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sdmmc3: sdmmc@48004000 {
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compatible = "st,stm32-sdmmc2";
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reg = <0x48004000 0x400>, <0x48005000 0x400>;
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reg-names = "sdmmc", "delay";
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clocks = <&rcc SDMMC3_K>;
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resets = <&rcc SDMMC3_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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rcc: rcc@50000000 {
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compatible = "syscon", "st,stm32mp1-rcc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0x50000000 0x1000>;
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};
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rcc_reboot: rcc-reboot@50000000 {
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compatible = "syscon-reboot";
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regmap = <&rcc>;
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offset = <0x404>;
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mask = <0x1>;
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};
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rng1: rng@54003000 {
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compatible = "st,stm32-rng";
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reg = <0x54003000 0x400>;
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clocks = <&rcc RNG1_K>;
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resets = <&rcc RNG1_R>;
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status = "disabled";
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};
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fmc_nand: fmc_nand@58002000 {
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compatible = "st,stm32mp1-fmc";
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reg = <0x58002000 0x1000>,
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<0x80000000 0x40000>,
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<0x81000000 0x40000>,
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<0x88000000 0x40000>,
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<0x89000000 0x40000>;
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clocks = <&rcc FMC_K>;
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resets = <&rcc FMC_R>;
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status = "disabled";
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};
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qspi: qspi@58003000 {
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compatible = "st,stm32f469-qspi";
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reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
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clocks = <&rcc QSPI_K>;
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status = "disabled";
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};
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sdmmc1: sdmmc@58005000 {
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compatible = "st,stm32-sdmmc2";
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reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
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reg-names = "sdmmc", "delay";
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clocks = <&rcc SDMMC1_K>;
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resets = <&rcc SDMMC1_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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sdmmc2: sdmmc@58007000 {
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compatible = "st,stm32-sdmmc2";
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reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
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reg-names = "sdmmc", "delay";
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clocks = <&rcc SDMMC2_K>;
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resets = <&rcc SDMMC2_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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iwdg2: iwdg@5a002000 {
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compatible = "st,stm32mp1-iwdg";
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reg = <0x5a002000 0x400>;
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clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
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clock-names = "pclk", "lsi";
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status = "disabled";
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};
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usart1: serial@5c000000 {
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compatible = "st,stm32h7-usart";
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reg = <0x5c000000 0x400>;
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clocks = <&rcc USART1_K>;
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status = "disabled";
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};
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i2c4: i2c@5c002000 {
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compatible = "st,stm32f7-i2c";
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reg = <0x5c002000 0x400>;
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clocks = <&rcc I2C4_K>;
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resets = <&rcc I2C4_R>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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rtc: rtc@5c004000 {
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compatible = "st,stm32mp1-rtc";
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reg = <0x5c004000 0x400>;
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clocks = <&rcc RTCAPB>, <&rcc RTC>;
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clock-names = "pclk", "rtc_ck";
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};
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};
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};
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