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202 lines
6.2 KiB
202 lines
6.2 KiB
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <string.h>
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#include <common/debug.h>
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#include <drivers/dw_ufs.h>
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#include <drivers/ufs.h>
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#include <lib/mmio.h>
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static int dwufs_phy_init(ufs_params_t *params)
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{
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uintptr_t base;
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unsigned int fsm0, fsm1;
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unsigned int data;
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int result;
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assert((params != NULL) && (params->reg_base != 0));
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base = params->reg_base;
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/* Unipro VS_MPHY disable */
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ufshc_dme_set(VS_MPHY_DISABLE_OFFSET, 0, VS_MPHY_DISABLE_MPHYDIS);
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ufshc_dme_set(PA_HS_SERIES_OFFSET, 0, 2);
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/* MPHY CBRATESEL */
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ufshc_dme_set(0x8114, 0, 1);
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/* MPHY CBOVRCTRL2 */
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ufshc_dme_set(0x8121, 0, 0x2d);
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/* MPHY CBOVRCTRL3 */
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ufshc_dme_set(0x8122, 0, 0x1);
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ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1);
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/* MPHY RXOVRCTRL4 rx0 */
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ufshc_dme_set(0x800d, 4, 0x58);
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/* MPHY RXOVRCTRL4 rx1 */
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ufshc_dme_set(0x800d, 5, 0x58);
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/* MPHY RXOVRCTRL5 rx0 */
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ufshc_dme_set(0x800e, 4, 0xb);
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/* MPHY RXOVRCTRL5 rx1 */
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ufshc_dme_set(0x800e, 5, 0xb);
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/* MPHY RXSQCONTROL rx0 */
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ufshc_dme_set(0x8009, 4, 0x1);
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/* MPHY RXSQCONTROL rx1 */
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ufshc_dme_set(0x8009, 5, 0x1);
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ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1);
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ufshc_dme_set(0x8113, 0, 0x1);
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ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1);
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ufshc_dme_set(RX_HS_G3_SYNC_LENGTH_CAP_OFFSET, 4, 0x4a);
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ufshc_dme_set(RX_HS_G3_SYNC_LENGTH_CAP_OFFSET, 5, 0x4a);
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ufshc_dme_set(RX_HS_G2_SYNC_LENGTH_CAP_OFFSET, 4, 0x4a);
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ufshc_dme_set(RX_HS_G2_SYNC_LENGTH_CAP_OFFSET, 5, 0x4a);
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ufshc_dme_set(RX_MIN_ACTIVATETIME_CAP_OFFSET, 4, 0x7);
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ufshc_dme_set(RX_MIN_ACTIVATETIME_CAP_OFFSET, 5, 0x7);
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ufshc_dme_set(TX_HIBERN8TIME_CAP_OFFSET, 0, 0x5);
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ufshc_dme_set(TX_HIBERN8TIME_CAP_OFFSET, 1, 0x5);
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ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1);
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result = ufshc_dme_get(VS_MPHY_DISABLE_OFFSET, 0, &data);
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assert((result == 0) && (data == VS_MPHY_DISABLE_MPHYDIS));
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/* enable Unipro VS MPHY */
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ufshc_dme_set(VS_MPHY_DISABLE_OFFSET, 0, 0);
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while (1) {
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result = ufshc_dme_get(TX_FSM_STATE_OFFSET, 0, &fsm0);
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assert(result == 0);
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result = ufshc_dme_get(TX_FSM_STATE_OFFSET, 1, &fsm1);
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assert(result == 0);
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if ((fsm0 == TX_FSM_STATE_HIBERN8) &&
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(fsm1 == TX_FSM_STATE_HIBERN8))
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break;
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}
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mmio_write_32(base + HCLKDIV, 0xE4);
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mmio_clrbits_32(base + AHIT, 0x3FF);
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ufshc_dme_set(PA_LOCAL_TX_LCC_ENABLE_OFFSET, 0, 0);
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ufshc_dme_set(VS_MK2_EXTN_SUPPORT_OFFSET, 0, 0);
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result = ufshc_dme_get(VS_MK2_EXTN_SUPPORT_OFFSET, 0, &data);
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assert((result == 0) && (data == 0));
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ufshc_dme_set(DL_AFC0_CREDIT_THRESHOLD_OFFSET, 0, 0);
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ufshc_dme_set(DL_TC0_OUT_ACK_THRESHOLD_OFFSET, 0, 0);
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ufshc_dme_set(DL_TC0_TX_FC_THRESHOLD_OFFSET, 0, 9);
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(void)result;
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return 0;
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}
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static int dwufs_phy_set_pwr_mode(ufs_params_t *params)
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{
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int result;
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unsigned int data, tx_lanes, rx_lanes;
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uintptr_t base;
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unsigned int flags;
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assert((params != NULL) && (params->reg_base != 0));
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base = params->reg_base;
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flags = params->flags;
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if ((flags & UFS_FLAGS_VENDOR_SKHYNIX) != 0U) {
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NOTICE("ufs: H**** device must set VS_DebugSaveConfigTime 0x10\n");
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/* VS_DebugSaveConfigTime */
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result = ufshc_dme_set(0xd0a0, 0x0, 0x10);
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assert(result == 0);
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/* sync length */
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result = ufshc_dme_set(0x1556, 0x0, 0x48);
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assert(result == 0);
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}
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result = ufshc_dme_get(PA_TACTIVATE_OFFSET, 0, &data);
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assert(result == 0);
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if (data < 7) {
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result = ufshc_dme_set(PA_TACTIVATE_OFFSET, 0, 7);
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assert(result == 0);
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}
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result = ufshc_dme_get(PA_CONNECTED_TX_DATA_LANES_OFFSET, 0, &tx_lanes);
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assert(result == 0);
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result = ufshc_dme_get(PA_CONNECTED_RX_DATA_LANES_OFFSET, 0, &rx_lanes);
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assert(result == 0);
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result = ufshc_dme_set(PA_TX_SKIP_OFFSET, 0, 0);
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assert(result == 0);
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result = ufshc_dme_set(PA_TX_GEAR_OFFSET, 0, 3);
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assert(result == 0);
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result = ufshc_dme_set(PA_RX_GEAR_OFFSET, 0, 3);
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assert(result == 0);
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result = ufshc_dme_set(PA_HS_SERIES_OFFSET, 0, 2);
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assert(result == 0);
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result = ufshc_dme_set(PA_TX_TERMINATION_OFFSET, 0, 1);
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assert(result == 0);
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result = ufshc_dme_set(PA_RX_TERMINATION_OFFSET, 0, 1);
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assert(result == 0);
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result = ufshc_dme_set(PA_SCRAMBLING_OFFSET, 0, 0);
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assert(result == 0);
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result = ufshc_dme_set(PA_ACTIVE_TX_DATA_LANES_OFFSET, 0, tx_lanes);
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assert(result == 0);
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result = ufshc_dme_set(PA_ACTIVE_RX_DATA_LANES_OFFSET, 0, rx_lanes);
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assert(result == 0);
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result = ufshc_dme_set(PA_PWR_MODE_USER_DATA0_OFFSET, 0, 8191);
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assert(result == 0);
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result = ufshc_dme_set(PA_PWR_MODE_USER_DATA1_OFFSET, 0, 65535);
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assert(result == 0);
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result = ufshc_dme_set(PA_PWR_MODE_USER_DATA2_OFFSET, 0, 32767);
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assert(result == 0);
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result = ufshc_dme_set(DME_FC0_PROTECTION_TIMEOUT_OFFSET, 0, 8191);
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assert(result == 0);
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result = ufshc_dme_set(DME_TC0_REPLAY_TIMEOUT_OFFSET, 0, 65535);
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assert(result == 0);
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result = ufshc_dme_set(DME_AFC0_REQ_TIMEOUT_OFFSET, 0, 32767);
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assert(result == 0);
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result = ufshc_dme_set(PA_PWR_MODE_USER_DATA3_OFFSET, 0, 8191);
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assert(result == 0);
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result = ufshc_dme_set(PA_PWR_MODE_USER_DATA4_OFFSET, 0, 65535);
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assert(result == 0);
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result = ufshc_dme_set(PA_PWR_MODE_USER_DATA5_OFFSET, 0, 32767);
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assert(result == 0);
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result = ufshc_dme_set(DME_FC1_PROTECTION_TIMEOUT_OFFSET, 0, 8191);
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assert(result == 0);
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result = ufshc_dme_set(DME_TC1_REPLAY_TIMEOUT_OFFSET, 0, 65535);
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assert(result == 0);
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result = ufshc_dme_set(DME_AFC1_REQ_TIMEOUT_OFFSET, 0, 32767);
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assert(result == 0);
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result = ufshc_dme_set(PA_PWR_MODE_OFFSET, 0, 0x11);
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assert(result == 0);
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do {
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data = mmio_read_32(base + IS);
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} while ((data & UFS_INT_UPMS) == 0);
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mmio_write_32(base + IS, UFS_INT_UPMS);
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data = mmio_read_32(base + HCS);
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if ((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL)
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INFO("ufs: change power mode success\n");
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else
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WARN("ufs: HCS.UPMCRS error, HCS:0x%x\n", data);
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(void)result;
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return 0;
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}
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static const ufs_ops_t dw_ufs_ops = {
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.phy_init = dwufs_phy_init,
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.phy_set_pwr_mode = dwufs_phy_set_pwr_mode,
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};
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int dw_ufs_init(dw_ufs_params_t *params)
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{
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ufs_params_t ufs_params;
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memset(&ufs_params, 0, sizeof(ufs_params));
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ufs_params.reg_base = params->reg_base;
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ufs_params.desc_base = params->desc_base;
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ufs_params.desc_size = params->desc_size;
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ufs_params.flags = params->flags;
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ufs_init(&dw_ufs_ops, &ufs_params);
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return 0;
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}
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