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133 lines
4.9 KiB
133 lines
4.9 KiB
/*
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* Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QOS_REG_H
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#define QOS_REG_H
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#define RCAR_QOS_NONE 3U
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#define RCAR_QOS_TYPE_DEFAULT 0U
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#define RCAR_DRAM_SPLIT_LINEAR 0U
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#define RCAR_DRAM_SPLIT_4CH 1U
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#define RCAR_DRAM_SPLIT_2CH 2U
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#define RCAR_DRAM_SPLIT_AUTO 3U
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#define RST_BASE (0xE6160000U)
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#define RST_MODEMR (RST_BASE + 0x0060U)
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#define DBSC_BASE 0xE6790000U
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#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
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#define DBSC_AXARB (DBSC_BASE + 0x0800U)
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#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
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#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
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#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
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#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
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#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
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#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
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#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
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#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
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#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
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#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
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#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
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#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
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#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
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#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
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#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
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#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
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#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
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#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
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#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
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#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
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#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
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#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
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#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
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#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
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#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
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#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
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#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
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#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
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#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
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#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
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#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
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#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
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#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
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#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
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#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
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#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
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#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U)
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#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U)
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#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
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#define AXI_BASE 0xE6784000U
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#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
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#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
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#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
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#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
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#define AXI_MMCR (AXI_BASE + 0x0300U)
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#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
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#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
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#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
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#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
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#define ADSPLCR0_SWP 0x0CU
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#define AXI_TR3CR 0xE67D100CU
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#define AXI_TR4CR 0xE67D1014U
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#define QOS_BASE0 0xE67E0000U
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#define QOSBW_FIX_QOS_BANK0 (QOS_BASE0 + 0x0000U)
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#define QOSBW_FIX_QOS_BANK1 (QOS_BASE0 + 0x1000U)
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#define QOSBW_BE_QOS_BANK0 (QOS_BASE0 + 0x2000U)
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#define QOSBW_BE_QOS_BANK1 (QOS_BASE0 + 0x3000U)
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#define QOSCTRL_SL_INIT (QOS_BASE0 + 0x8000U)
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#define QOSCTRL_REF_ARS (QOS_BASE0 + 0x8004U)
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#define QOSCTRL_STATQC (QOS_BASE0 + 0x8008U)
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#define QOS_BASE1 0xE67F0000U
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#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
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#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
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#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
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#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
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#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
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#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
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#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
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#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
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#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
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#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
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#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
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#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
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#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
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#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
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#define GPU_ACT_GRD 0xFD820808U
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#define GPU_ACT0 0xFD820800U
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#define GPU_ACT1 0xFD821800U
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#define GPU_ACT2 0xFD822800U
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#define GPU_ACT3 0xFD823800U
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#define GPU_ACT4 0xFD824800U
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#define GPU_ACT5 0xFD825800U
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#define GPU_ACT6 0xFD826800U
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#define GPU_ACT7 0xFD827800U
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#define RT_ACT0 0xFFC50800U
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#define RT_ACT1 0xFFC51800U
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#define CPU_ACT0 0xF1300800U
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#define CPU_ACT1 0xF1340800U
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#define CPU_ACT2 0xF1380800U
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#define CPU_ACT3 0xF13C0800U
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#define RCAR_REWT_TRAINING_DISABLE 0U
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#define RCAR_REWT_TRAINING_ENABLE 1U
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#define QOSWT_FIX_WTQOS_BANK0 (QOSBW_FIX_QOS_BANK0 + 0x0800U)
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#define QOSWT_FIX_WTQOS_BANK1 (QOSBW_FIX_QOS_BANK1 + 0x0800U)
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#define QOSWT_BE_WTQOS_BANK0 (QOSBW_BE_QOS_BANK0 + 0x0800U)
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#define QOSWT_BE_WTQOS_BANK1 (QOSBW_BE_QOS_BANK1 + 0x0800U)
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#define QOSWT_WTEN (QOS_BASE0 + 0x8030U)
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#define QOSWT_WTREF (QOS_BASE0 + 0x8034U)
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#define QOSWT_WTSET0 (QOS_BASE0 + 0x8038U)
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#define QOSWT_WTSET1 (QOS_BASE0 + 0x803CU)
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#endif /* QOS_REG_H */
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