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345 lines
13 KiB
345 lines
13 KiB
/*
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __ZYNQMP_DEF_H__
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#define __ZYNQMP_DEF_H__
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#include <common_def.h>
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#define ZYNQMP_CONSOLE_ID_cadence 1
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#define ZYNQMP_CONSOLE_ID_cadence0 1
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#define ZYNQMP_CONSOLE_ID_cadence1 2
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#define ZYNQMP_CONSOLE_ID_dcc 3
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#define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
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/* Firmware Image Package */
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#define ZYNQMP_PRIMARY_CPU 0
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/* Memory location options for Shared data and TSP in ZYNQMP */
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#define ZYNQMP_IN_TRUSTED_SRAM 0
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#define ZYNQMP_IN_TRUSTED_DRAM 1
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/*******************************************************************************
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* ZYNQMP memory map related constants
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******************************************************************************/
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/* Aggregate of all devices in the first GB */
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#define DEVICE0_BASE U(0xFF000000)
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#define DEVICE0_SIZE U(0x00E00000)
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#define DEVICE1_BASE U(0xF9000000)
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#define DEVICE1_SIZE U(0x00800000)
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/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
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#define CRF_APB_BASE U(0xFD1A0000)
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#define CRF_APB_SIZE U(0x00600000)
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#define CRF_APB_CLK_BASE U(0xFD1A0020)
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/* CRF registers and bitfields */
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#define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104)
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#define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0)
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#define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10)
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/* CRL registers and bitfields */
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#define CRL_APB_BASE U(0xFF5E0000)
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#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200)
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#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218)
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#define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C)
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#define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250))
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#define CRL_APB_CLK_BASE U(0xFF5E0020)
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#define CRL_APB_RPU_AMBA_RESET (U(1) << 2)
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#define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3)
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#define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4)
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#define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0)
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#define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0)
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#define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9)
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#define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1)
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#define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << CRL_APB_BOOT_ENABLE_PIN_1_SHIFT)
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#define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
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#define ZYNQMP_BOOTMODE_JTAG U(0)
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#define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \
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CRL_APB_BOOT_DRIVE_PIN_1)
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#define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1
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/* system counter registers and bitfields */
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#define IOU_SCNTRS_BASE 0xFF260000
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#define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20)
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/* APU registers and bitfields */
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#define APU_BASE 0xFD5C0000
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#define APU_CONFIG_0 (APU_BASE + 0x20)
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#define APU_RVBAR_L_0 (APU_BASE + 0x40)
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#define APU_RVBAR_H_0 (APU_BASE + 0x44)
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#define APU_PWRCTL (APU_BASE + 0x90)
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#define APU_CONFIG_0_VINITHI_SHIFT 8
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#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1
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#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2
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#define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4
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#define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8
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/* PMU registers and bitfields */
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#define PMU_GLOBAL_BASE 0xFFD80000
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#define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0)
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#define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48)
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#define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110)
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#define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118)
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#define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c)
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#define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120)
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#define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4)
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define PLAT_ARM_CCI_BASE 0xFD6E0000
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#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3
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#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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#define BASE_GICD_BASE 0xF9010000
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#define BASE_GICC_BASE 0xF9020000
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#define BASE_GICH_BASE 0xF9040000
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#define BASE_GICV_BASE 0xF9060000
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#if ZYNQMP_WDT_RESTART
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#define IRQ_SEC_IPI_APU 67
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#define IRQ_TTC3_1 77
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#define TTC3_BASE_ADDR 0xFF140000
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#define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54)
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#define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60)
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#endif
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#define ARM_IRQ_SEC_PHY_TIMER 29
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#define ARM_IRQ_SEC_SGI_0 8
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#define ARM_IRQ_SEC_SGI_1 9
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#define ARM_IRQ_SEC_SGI_2 10
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#define ARM_IRQ_SEC_SGI_3 11
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#define ARM_IRQ_SEC_SGI_4 12
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#define ARM_IRQ_SEC_SGI_5 13
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#define ARM_IRQ_SEC_SGI_6 14
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#define ARM_IRQ_SEC_SGI_7 15
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#define MAX_INTR_EL3 128
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define ZYNQMP_UART0_BASE 0xFF000000
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#define ZYNQMP_UART1_BASE 0xFF010000
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#if ZYNQMP_CONSOLE_IS(cadence)
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# define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE
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#elif ZYNQMP_CONSOLE_IS(cadence1)
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# define ZYNQMP_UART_BASE ZYNQMP_UART1_BASE
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#else
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# error "invalid ZYNQMP_CONSOLE"
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#endif
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#define PLAT_ARM_CRASH_UART_BASE ZYNQMP_UART_BASE
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/* impossible to call C routine how it is done now - hardcode any value */
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ 100000000 /* FIXME */
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/* Must be non zero */
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#define ZYNQMP_UART_BAUDRATE 115200
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#define ARM_CONSOLE_BAUDRATE ZYNQMP_UART_BAUDRATE
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/* Silicon version detection */
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#define ZYNQMP_SILICON_VER_MASK 0xF000
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#define ZYNQMP_SILICON_VER_SHIFT 12
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#define ZYNQMP_CSU_VERSION_SILICON 0
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#define ZYNQMP_CSU_VERSION_QEMU 3
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#define ZYNQMP_RTL_VER_MASK 0xFF0
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#define ZYNQMP_RTL_VER_SHIFT 4
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#define ZYNQMP_PS_VER_MASK 0xF
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#define ZYNQMP_PS_VER_SHIFT 0
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#define ZYNQMP_CSU_BASEADDR 0xFFCA0000
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#define ZYNQMP_CSU_IDCODE_OFFSET 0x40
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#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0
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#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFF << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
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#define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093
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#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
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#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << \
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ZYNQMP_CSU_IDCODE_SVD_SHIFT)
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#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
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#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xF << ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
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#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19
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#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3 << ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
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#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21
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#define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7F << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
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#define ZYNQMP_CSU_IDCODE_FAMILY 0x23
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#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28
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#define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xF << ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
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#define ZYNQMP_CSU_IDCODE_REVISION 0
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#define ZYNQMP_CSU_VERSION_OFFSET 0x44
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/* Efuse */
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#define EFUSE_BASEADDR 0xFFCC0000
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#define EFUSE_IPDISABLE_OFFSET 0x1018
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#define EFUSE_IPDISABLE_VERSION 0x1FFU
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#define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20
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/* Access control register defines */
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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#define FPD_SLCR_BASEADDR U(0xFD610000)
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#define IOU_SLCR_BASEADDR U(0xFF180000)
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#define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000)
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#define ZYNQMP_RPU0_CFG U(0xFF9A0100)
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#define ZYNQMP_RPU1_CFG U(0xFF9A0200)
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#define ZYNQMP_SLSPLIT_MASK U(0x08)
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#define ZYNQMP_TCM_COMB_MASK U(0x40)
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#define ZYNQMP_SLCLAMP_MASK U(0x10)
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#define ZYNQMP_VINITHI_MASK U(0x04)
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/* Tap delay bypass */
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#define IOU_TAPDLY_BYPASS U(0XFF180390)
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#define TAP_DELAY_MASK U(0x7)
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/* SGMII mode */
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#define IOU_GEM_CTRL U(0xFF180360)
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#define IOU_GEM_CLK_CTRL U(0xFF180308)
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#define SGMII_SD_MASK U(0x3)
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#define SGMII_SD_OFFSET U(2)
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#define SGMII_PCS_SD_0 U(0x0)
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#define SGMII_PCS_SD_1 U(0x1)
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#define SGMII_PCS_SD_PHY U(0x2)
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#define GEM_SGMII_MASK U(0x4)
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#define GEM_CLK_CTRL_MASK U(0xF)
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#define GEM_CLK_CTRL_OFFSET U(5)
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#define GEM_RX_SRC_SEL_GTR U(0x1)
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#define GEM_SGMII_MODE U(0x4)
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/* SD DLL reset */
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#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
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#define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004)
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#define ZYNQMP_SD0_DLL_RST U(0x00000004)
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#define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000)
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#define ZYNQMP_SD1_DLL_RST U(0x00040000)
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/* SD tap delay */
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#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
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#define ZYNQMP_SD_ITAP_DLY U(0xFF180314)
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#define ZYNQMP_SD_OTAP_DLY U(0xFF180318)
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#define ZYNQMP_SD_TAP_OFFSET U(16)
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#define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200)
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#define ZYNQMP_SD_ITAPCHGWIN U(0x200)
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#define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100)
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#define ZYNQMP_SD_ITAPDLYENA U(0x100)
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#define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF)
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#define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F)
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#define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40)
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#define ZYNQMP_SD_OTAPDLYENA U(0x40)
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/* Clock control registers */
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/* Full power domain clocks */
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#define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00)
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#define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c)
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#define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18)
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#define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24)
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#define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28)
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#define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c)
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#define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30)
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/* Peripheral clocks */
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#define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40)
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#define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44)
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#define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48)
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#define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50)
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#define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54)
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#define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c)
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#define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60)
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#define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64)
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#define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80)
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#define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94)
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#define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98)
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#define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c)
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#define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0)
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#define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4)
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#define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8)
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#define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8)
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/* Low power domain clocks */
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#define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00)
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#define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10)
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#define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20)
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#define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24)
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#define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28)
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/* Peripheral clocks */
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#define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c)
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#define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30)
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#define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34)
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#define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38)
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#define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c)
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#define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40)
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#define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44)
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#define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48)
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#define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c)
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#define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50)
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#define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54)
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#define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58)
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#define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c)
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#define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60)
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#define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64)
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#define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68)
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#define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70)
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#define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c)
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#define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80)
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#define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84)
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#define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88)
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#define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c)
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#define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90)
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#define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94)
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#define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98)
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#define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0)
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#define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4)
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#define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8)
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#define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac)
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#define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4)
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#define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc)
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#define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4)
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#define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc)
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#define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0)
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#define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4)
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#define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8)
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#define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100)
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#define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104)
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#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108)
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#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
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#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
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#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100)
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/* Global general storage register base address */
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#define GGS_BASEADDR (0xFFD80030U)
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#define GGS_NUM_REGS U(4)
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/* Persistent global general storage register base address */
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#define PGGS_BASEADDR (0xFFD80050U)
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#define PGGS_NUM_REGS U(4)
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/* Warm restart boot health status register and mask */
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#define PM_BOOT_HEALTH_STATUS_REG (GGS_BASEADDR + U(0x10))
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#define PM_BOOT_HEALTH_STATUS_MASK U(0x01)
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/*AFI registers */
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#define AFIFM6_WRCTRL U(13)
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#define FABRIC_WIDTH U(3)
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#endif /* __ZYNQMP_DEF_H__ */
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