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211 lines
6.4 KiB
211 lines
6.4 KiB
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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.globl flush_dcache_range
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.globl inv_dcache_range
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.globl dcsw_op_louis
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.globl dcsw_op_all
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.globl dcsw_op_level1
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.globl dcsw_op_level2
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.globl dcsw_op_level3
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/* ------------------------------------------
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* Clean+Invalidate from base address till
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* size. 'x0' = addr, 'x1' = size
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* ------------------------------------------
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*/
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func flush_dcache_range
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dcache_line_size x2, x3
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add x1, x0, x1
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sub x3, x2, #1
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bic x0, x0, x3
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flush_loop:
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dc civac, x0
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add x0, x0, x2
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cmp x0, x1
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b.lo flush_loop
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dsb sy
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ret
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/* ------------------------------------------
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* Invalidate from base address till
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* size. 'x0' = addr, 'x1' = size
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* ------------------------------------------
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*/
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func inv_dcache_range
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dcache_line_size x2, x3
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add x1, x0, x1
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sub x3, x2, #1
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bic x0, x0, x3
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inv_loop:
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dc ivac, x0
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add x0, x0, x2
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cmp x0, x1
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b.lo inv_loop
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dsb sy
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ret
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/* ---------------------------------------------------------------
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* Data cache operations by set/way to the level specified
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* x3: The last cache level to operate on
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* x9: clidr_el1
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* x10: The cache level to begin operation from
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* and will carry out the operation on each data cache from level 0
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* to the level in x3 in sequence
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*
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* The dcsw_op macro sets up the x3 and x9 parameters based on
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* clidr_el1 cache information before invoking the main function
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* ---------------------------------------------------------------
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*/
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.macro dcsw_op shift, fw, ls
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mrs x9, clidr_el1
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ubfx x3, x9, \shift, \fw
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lsl x3, x3, \ls
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mov x10, xzr
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b do_dcsw_op
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.endm
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func do_dcsw_op
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cbz x3, exit
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adr x14, dcsw_loop_table // compute inner loop address
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add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions
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mov x0, x9
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mov w8, #1
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loop1:
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add x2, x10, x10, lsr #1 // work out 3x current cache level
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lsr x1, x0, x2 // extract cache type bits from clidr
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and x1, x1, #7 // mask the bits for current cache only
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cmp x1, #2 // see what cache we have at this level
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b.lt level_done // nothing to do if no cache or icache
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msr csselr_el1, x10 // select current cache level in csselr
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isb // isb to sych the new cssr&csidr
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mrs x1, ccsidr_el1 // read the new ccsidr
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and x2, x1, #7 // extract the length of the cache lines
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add x2, x2, #4 // add 4 (line length offset)
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ubfx x4, x1, #3, #10 // maximum way number
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clz w5, w4 // bit position of way size increment
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lsl w9, w4, w5 // w9 = aligned max way number
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lsl w16, w8, w5 // w16 = way number loop decrement
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orr w9, w10, w9 // w9 = combine way and cache number
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ubfx w6, w1, #13, #15 // w6 = max set number
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lsl w17, w8, w2 // w17 = set number loop decrement
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dsb sy // barrier before we start this level
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br x14 // jump to DC operation specific loop
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.macro dcsw_loop _op
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loop2_\_op:
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lsl w7, w6, w2 // w7 = aligned max set number
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loop3_\_op:
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orr w11, w9, w7 // combine cache, way and set number
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dc \_op, x11
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subs w7, w7, w17 // decrement set number
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b.ge loop3_\_op
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subs x9, x9, x16 // decrement way number
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b.ge loop2_\_op
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b level_done
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.endm
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level_done:
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add x10, x10, #2 // increment cache number
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cmp x3, x10
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b.gt loop1
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msr csselr_el1, xzr // select cache level 0 in csselr
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dsb sy // barrier to complete final cache operation
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isb
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exit:
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ret
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dcsw_loop_table:
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dcsw_loop isw
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dcsw_loop cisw
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dcsw_loop csw
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func dcsw_op_louis
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dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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func dcsw_op_all
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dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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/* ---------------------------------------------------------------
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* Helper macro for data cache operations by set/way for the
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* level specified
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* ---------------------------------------------------------------
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*/
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.macro dcsw_op_level level
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mrs x9, clidr_el1
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mov x3, \level
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sub x10, x3, #2
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b do_dcsw_op
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.endm
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 1 cache
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level1
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dcsw_op_level #(1 << LEVEL_SHIFT)
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 2 cache
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level2
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dcsw_op_level #(2 << LEVEL_SHIFT)
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 3 cache
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level3
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dcsw_op_level #(3 << LEVEL_SHIFT)
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