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432 lines
11 KiB
432 lines
11 KiB
/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <string.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/mmc.h>
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#include <drivers/synopsys/dw_mmc.h>
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#include <lib/mmio.h>
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#define DWMMC_CTRL (0x00)
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#define CTRL_IDMAC_EN (1 << 25)
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#define CTRL_DMA_EN (1 << 5)
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#define CTRL_INT_EN (1 << 4)
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#define CTRL_DMA_RESET (1 << 2)
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#define CTRL_FIFO_RESET (1 << 1)
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#define CTRL_RESET (1 << 0)
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#define CTRL_RESET_ALL (CTRL_DMA_RESET | CTRL_FIFO_RESET | \
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CTRL_RESET)
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#define DWMMC_PWREN (0x04)
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#define DWMMC_CLKDIV (0x08)
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#define DWMMC_CLKSRC (0x0c)
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#define DWMMC_CLKENA (0x10)
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#define DWMMC_TMOUT (0x14)
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#define DWMMC_CTYPE (0x18)
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#define CTYPE_8BIT (1 << 16)
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#define CTYPE_4BIT (1)
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#define CTYPE_1BIT (0)
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#define DWMMC_BLKSIZ (0x1c)
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#define DWMMC_BYTCNT (0x20)
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#define DWMMC_INTMASK (0x24)
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#define INT_EBE (1 << 15)
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#define INT_SBE (1 << 13)
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#define INT_HLE (1 << 12)
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#define INT_FRUN (1 << 11)
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#define INT_DRT (1 << 9)
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#define INT_RTO (1 << 8)
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#define INT_DCRC (1 << 7)
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#define INT_RCRC (1 << 6)
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#define INT_RXDR (1 << 5)
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#define INT_TXDR (1 << 4)
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#define INT_DTO (1 << 3)
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#define INT_CMD_DONE (1 << 2)
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#define INT_RE (1 << 1)
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#define DWMMC_CMDARG (0x28)
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#define DWMMC_CMD (0x2c)
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#define CMD_START (1 << 31)
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#define CMD_USE_HOLD_REG (1 << 29) /* 0 if SDR50/100 */
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#define CMD_UPDATE_CLK_ONLY (1 << 21)
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#define CMD_SEND_INIT (1 << 15)
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#define CMD_STOP_ABORT_CMD (1 << 14)
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#define CMD_WAIT_PRVDATA_COMPLETE (1 << 13)
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#define CMD_WRITE (1 << 10)
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#define CMD_DATA_TRANS_EXPECT (1 << 9)
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#define CMD_CHECK_RESP_CRC (1 << 8)
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#define CMD_RESP_LEN (1 << 7)
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#define CMD_RESP_EXPECT (1 << 6)
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#define CMD(x) (x & 0x3f)
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#define DWMMC_RESP0 (0x30)
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#define DWMMC_RESP1 (0x34)
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#define DWMMC_RESP2 (0x38)
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#define DWMMC_RESP3 (0x3c)
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#define DWMMC_RINTSTS (0x44)
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#define DWMMC_STATUS (0x48)
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#define STATUS_DATA_BUSY (1 << 9)
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#define DWMMC_FIFOTH (0x4c)
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#define FIFOTH_TWMARK(x) (x & 0xfff)
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#define FIFOTH_RWMARK(x) ((x & 0x1ff) << 16)
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#define FIFOTH_DMA_BURST_SIZE(x) ((x & 0x7) << 28)
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#define DWMMC_DEBNCE (0x64)
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#define DWMMC_BMOD (0x80)
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#define BMOD_ENABLE (1 << 7)
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#define BMOD_FB (1 << 1)
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#define BMOD_SWRESET (1 << 0)
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#define DWMMC_DBADDR (0x88)
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#define DWMMC_IDSTS (0x8c)
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#define DWMMC_IDINTEN (0x90)
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#define DWMMC_CARDTHRCTL (0x100)
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#define CARDTHRCTL_RD_THR(x) ((x & 0xfff) << 16)
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#define CARDTHRCTL_RD_THR_EN (1 << 0)
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#define IDMAC_DES0_DIC (1 << 1)
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#define IDMAC_DES0_LD (1 << 2)
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#define IDMAC_DES0_FS (1 << 3)
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#define IDMAC_DES0_CH (1 << 4)
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#define IDMAC_DES0_ER (1 << 5)
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#define IDMAC_DES0_CES (1 << 30)
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#define IDMAC_DES0_OWN (1 << 31)
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#define IDMAC_DES1_BS1(x) ((x) & 0x1fff)
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#define IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13)
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#define DWMMC_DMA_MAX_BUFFER_SIZE (512 * 8)
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#define DWMMC_8BIT_MODE (1 << 6)
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#define DWMMC_ADDRESS_MASK U(0x0f)
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#define TIMEOUT 100000
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struct dw_idmac_desc {
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unsigned int des0;
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unsigned int des1;
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unsigned int des2;
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unsigned int des3;
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};
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static void dw_init(void);
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static int dw_send_cmd(struct mmc_cmd *cmd);
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static int dw_set_ios(unsigned int clk, unsigned int width);
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static int dw_prepare(int lba, uintptr_t buf, size_t size);
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static int dw_read(int lba, uintptr_t buf, size_t size);
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static int dw_write(int lba, uintptr_t buf, size_t size);
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static const struct mmc_ops dw_mmc_ops = {
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.init = dw_init,
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.send_cmd = dw_send_cmd,
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.set_ios = dw_set_ios,
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.prepare = dw_prepare,
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.read = dw_read,
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.write = dw_write,
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};
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static dw_mmc_params_t dw_params;
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static void dw_update_clk(void)
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{
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unsigned int data;
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mmio_write_32(dw_params.reg_base + DWMMC_CMD,
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CMD_WAIT_PRVDATA_COMPLETE | CMD_UPDATE_CLK_ONLY |
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CMD_START);
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while (1) {
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data = mmio_read_32(dw_params.reg_base + DWMMC_CMD);
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if ((data & CMD_START) == 0)
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break;
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data = mmio_read_32(dw_params.reg_base + DWMMC_RINTSTS);
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assert((data & INT_HLE) == 0);
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}
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}
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static void dw_set_clk(int clk)
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{
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unsigned int data;
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int div;
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assert(clk > 0);
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for (div = 1; div < 256; div++) {
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if ((dw_params.clk_rate / (2 * div)) <= clk) {
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break;
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}
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}
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assert(div < 256);
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/* wait until controller is idle */
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do {
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data = mmio_read_32(dw_params.reg_base + DWMMC_STATUS);
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} while (data & STATUS_DATA_BUSY);
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/* disable clock before change clock rate */
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mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 0);
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dw_update_clk();
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mmio_write_32(dw_params.reg_base + DWMMC_CLKDIV, div);
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dw_update_clk();
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/* enable clock */
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mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 1);
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mmio_write_32(dw_params.reg_base + DWMMC_CLKSRC, 0);
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dw_update_clk();
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}
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static void dw_init(void)
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{
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unsigned int data;
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uintptr_t base;
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assert((dw_params.reg_base & MMC_BLOCK_MASK) == 0);
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base = dw_params.reg_base;
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mmio_write_32(base + DWMMC_PWREN, 1);
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mmio_write_32(base + DWMMC_CTRL, CTRL_RESET_ALL);
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do {
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data = mmio_read_32(base + DWMMC_CTRL);
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} while (data);
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/* enable DMA in CTRL */
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data = CTRL_INT_EN | CTRL_DMA_EN | CTRL_IDMAC_EN;
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mmio_write_32(base + DWMMC_CTRL, data);
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mmio_write_32(base + DWMMC_RINTSTS, ~0);
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mmio_write_32(base + DWMMC_INTMASK, 0);
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mmio_write_32(base + DWMMC_TMOUT, ~0);
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mmio_write_32(base + DWMMC_IDINTEN, ~0);
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mmio_write_32(base + DWMMC_BLKSIZ, MMC_BLOCK_SIZE);
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mmio_write_32(base + DWMMC_BYTCNT, 256 * 1024);
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mmio_write_32(base + DWMMC_DEBNCE, 0x00ffffff);
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mmio_write_32(base + DWMMC_BMOD, BMOD_SWRESET);
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do {
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data = mmio_read_32(base + DWMMC_BMOD);
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} while (data & BMOD_SWRESET);
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/* enable DMA in BMOD */
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data |= BMOD_ENABLE | BMOD_FB;
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mmio_write_32(base + DWMMC_BMOD, data);
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udelay(100);
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dw_set_clk(MMC_BOOT_CLK_RATE);
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udelay(100);
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}
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static int dw_send_cmd(struct mmc_cmd *cmd)
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{
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unsigned int op, data, err_mask;
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uintptr_t base;
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int timeout;
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assert(cmd);
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base = dw_params.reg_base;
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switch (cmd->cmd_idx) {
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case 0:
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op = CMD_SEND_INIT;
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break;
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case 12:
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op = CMD_STOP_ABORT_CMD;
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break;
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case 13:
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op = CMD_WAIT_PRVDATA_COMPLETE;
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break;
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case 8:
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if (dw_params.mmc_dev_type == MMC_IS_EMMC)
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op = CMD_DATA_TRANS_EXPECT | CMD_WAIT_PRVDATA_COMPLETE;
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else
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op = CMD_WAIT_PRVDATA_COMPLETE;
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break;
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case 17:
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case 18:
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op = CMD_DATA_TRANS_EXPECT | CMD_WAIT_PRVDATA_COMPLETE;
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break;
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case 24:
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case 25:
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op = CMD_WRITE | CMD_DATA_TRANS_EXPECT |
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CMD_WAIT_PRVDATA_COMPLETE;
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break;
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case 51:
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op = CMD_DATA_TRANS_EXPECT;
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break;
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default:
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op = 0;
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break;
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}
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op |= CMD_USE_HOLD_REG | CMD_START;
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switch (cmd->resp_type) {
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case 0:
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break;
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case MMC_RESPONSE_R2:
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op |= CMD_RESP_EXPECT | CMD_CHECK_RESP_CRC |
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CMD_RESP_LEN;
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break;
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case MMC_RESPONSE_R3:
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op |= CMD_RESP_EXPECT;
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break;
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default:
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op |= CMD_RESP_EXPECT | CMD_CHECK_RESP_CRC;
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break;
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}
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timeout = TIMEOUT;
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do {
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data = mmio_read_32(base + DWMMC_STATUS);
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if (--timeout <= 0)
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panic();
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} while (data & STATUS_DATA_BUSY);
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mmio_write_32(base + DWMMC_RINTSTS, ~0);
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mmio_write_32(base + DWMMC_CMDARG, cmd->cmd_arg);
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mmio_write_32(base + DWMMC_CMD, op | cmd->cmd_idx);
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err_mask = INT_EBE | INT_HLE | INT_RTO | INT_RCRC | INT_RE |
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INT_DCRC | INT_DRT | INT_SBE;
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timeout = TIMEOUT;
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do {
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udelay(500);
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data = mmio_read_32(base + DWMMC_RINTSTS);
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if (data & err_mask)
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return -EIO;
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if (data & INT_DTO)
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break;
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if (--timeout == 0) {
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ERROR("%s, RINTSTS:0x%x\n", __func__, data);
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panic();
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}
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} while (!(data & INT_CMD_DONE));
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if (op & CMD_RESP_EXPECT) {
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cmd->resp_data[0] = mmio_read_32(base + DWMMC_RESP0);
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if (op & CMD_RESP_LEN) {
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cmd->resp_data[1] = mmio_read_32(base + DWMMC_RESP1);
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cmd->resp_data[2] = mmio_read_32(base + DWMMC_RESP2);
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cmd->resp_data[3] = mmio_read_32(base + DWMMC_RESP3);
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}
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}
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return 0;
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}
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static int dw_set_ios(unsigned int clk, unsigned int width)
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{
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switch (width) {
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case MMC_BUS_WIDTH_1:
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mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_1BIT);
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break;
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case MMC_BUS_WIDTH_4:
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mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_4BIT);
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break;
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case MMC_BUS_WIDTH_8:
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mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_8BIT);
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break;
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default:
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assert(0);
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break;
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}
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dw_set_clk(clk);
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return 0;
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}
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static int dw_prepare(int lba, uintptr_t buf, size_t size)
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{
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struct dw_idmac_desc *desc;
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int desc_cnt, i, last;
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uintptr_t base;
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assert(((buf & DWMMC_ADDRESS_MASK) == 0) &&
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(dw_params.desc_size > 0) &&
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((dw_params.reg_base & MMC_BLOCK_MASK) == 0) &&
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((dw_params.desc_base & MMC_BLOCK_MASK) == 0) &&
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((dw_params.desc_size & MMC_BLOCK_MASK) == 0));
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flush_dcache_range(buf, size);
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desc_cnt = (size + DWMMC_DMA_MAX_BUFFER_SIZE - 1) /
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DWMMC_DMA_MAX_BUFFER_SIZE;
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assert(desc_cnt * sizeof(struct dw_idmac_desc) < dw_params.desc_size);
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base = dw_params.reg_base;
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desc = (struct dw_idmac_desc *)dw_params.desc_base;
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mmio_write_32(base + DWMMC_BYTCNT, size);
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if (size < MMC_BLOCK_SIZE)
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mmio_write_32(base + DWMMC_BLKSIZ, size);
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else
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mmio_write_32(base + DWMMC_BLKSIZ, MMC_BLOCK_SIZE);
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mmio_write_32(base + DWMMC_RINTSTS, ~0);
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for (i = 0; i < desc_cnt; i++) {
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desc[i].des0 = IDMAC_DES0_OWN | IDMAC_DES0_CH | IDMAC_DES0_DIC;
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desc[i].des1 = IDMAC_DES1_BS1(DWMMC_DMA_MAX_BUFFER_SIZE);
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desc[i].des2 = buf + DWMMC_DMA_MAX_BUFFER_SIZE * i;
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desc[i].des3 = dw_params.desc_base +
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(sizeof(struct dw_idmac_desc)) * (i + 1);
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}
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/* first descriptor */
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desc->des0 |= IDMAC_DES0_FS;
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/* last descriptor */
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last = desc_cnt - 1;
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(desc + last)->des0 |= IDMAC_DES0_LD;
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(desc + last)->des0 &= ~(IDMAC_DES0_DIC | IDMAC_DES0_CH);
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(desc + last)->des1 = IDMAC_DES1_BS1(size - (last *
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DWMMC_DMA_MAX_BUFFER_SIZE));
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/* set next descriptor address as 0 */
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(desc + last)->des3 = 0;
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mmio_write_32(base + DWMMC_DBADDR, dw_params.desc_base);
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flush_dcache_range(dw_params.desc_base,
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desc_cnt * DWMMC_DMA_MAX_BUFFER_SIZE);
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return 0;
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}
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static int dw_read(int lba, uintptr_t buf, size_t size)
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{
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uint32_t data = 0;
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int timeout = TIMEOUT;
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do {
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data = mmio_read_32(dw_params.reg_base + DWMMC_RINTSTS);
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udelay(50);
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} while (!(data & INT_DTO) && timeout-- > 0);
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inv_dcache_range(buf, size);
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return 0;
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}
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static int dw_write(int lba, uintptr_t buf, size_t size)
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{
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return 0;
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}
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void dw_mmc_init(dw_mmc_params_t *params, struct mmc_device_info *info)
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{
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assert((params != 0) &&
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((params->reg_base & MMC_BLOCK_MASK) == 0) &&
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((params->desc_base & MMC_BLOCK_MASK) == 0) &&
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((params->desc_size & MMC_BLOCK_MASK) == 0) &&
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(params->desc_size > 0) &&
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(params->clk_rate > 0) &&
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((params->bus_width == MMC_BUS_WIDTH_1) ||
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(params->bus_width == MMC_BUS_WIDTH_4) ||
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(params->bus_width == MMC_BUS_WIDTH_8)));
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memcpy(&dw_params, params, sizeof(dw_mmc_params_t));
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mmio_write_32(dw_params.reg_base + DWMMC_FIFOTH, 0x103ff);
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dw_params.mmc_dev_type = info->mmc_dev_type;
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mmc_init(&dw_mmc_ops, params->clk_rate, params->bus_width,
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params->flags, info);
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}
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