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108 lines
3.3 KiB
108 lines
3.3 KiB
/*
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* Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <common/bl_common.h>
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#include <el3_common_macros.S>
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.globl bl1_entrypoint
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.globl bl1_run_bl2_in_root
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/* -----------------------------------------------------
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* bl1_entrypoint() is the entry point into the trusted
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* firmware code when a cpu is released from warm or
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* cold reset.
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* -----------------------------------------------------
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*/
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func bl1_entrypoint
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/* ---------------------------------------------------------------------
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* If the reset address is programmable then bl1_entrypoint() is
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* executed only on the cold boot path. Therefore, we can skip the warm
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* boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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el3_entrypoint_common \
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_init_sctlr=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl1_exceptions \
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_pie_fixup_size=0
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/* --------------------------------------------------------------------
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* Perform BL1 setup
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* --------------------------------------------------------------------
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*/
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bl bl1_setup
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#if ENABLE_PAUTH
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/* --------------------------------------------------------------------
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* Program APIAKey_EL1 and enable pointer authentication.
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* --------------------------------------------------------------------
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*/
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bl pauth_init_enable_el3
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#endif /* ENABLE_PAUTH */
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/* --------------------------------------------------------------------
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* Initialize platform and jump to our c-entry point
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* for this type of reset.
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* --------------------------------------------------------------------
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*/
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bl bl1_main
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#if ENABLE_PAUTH
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/* --------------------------------------------------------------------
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* Disable pointer authentication before jumping to next boot image.
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* --------------------------------------------------------------------
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*/
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bl pauth_disable_el3
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#endif /* ENABLE_PAUTH */
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/* --------------------------------------------------
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* Do the transition to next boot image.
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* --------------------------------------------------
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*/
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#if ENABLE_RME
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b bl1_run_bl2_in_root
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#else
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b el3_exit
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#endif
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endfunc bl1_entrypoint
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/* -----------------------------------------------------
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* void bl1_run_bl2_in_root();
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* This function runs BL2 in root/EL3 when RME is enabled.
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* -----------------------------------------------------
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*/
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func bl1_run_bl2_in_root
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/* read bl2_ep_info */
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adrp x20, bl2_ep_info
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add x20, x20, :lo12:bl2_ep_info
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ldr x20, [x20]
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/* ---------------------------------------------
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* MMU needs to be disabled because BL2 executes
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* in EL3. It will initialize the address space
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* according to its own requirements.
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* ---------------------------------------------
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*/
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bl disable_mmu_icache_el3
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tlbi alle3
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ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
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msr elr_el3, x0
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msr spsr_el3, x1
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ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
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ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
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ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
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ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
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exception_return
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endfunc bl1_run_bl2_in_root
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