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89 lines
2.5 KiB
89 lines
2.5 KiB
/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/arm/css/sds.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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#include "n1sdp_def.h"
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#include <plat/arm/common/plat_arm.h>
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struct n1sdp_plat_info {
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bool multichip_mode;
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uint8_t secondary_count;
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uint8_t local_ddr_size;
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uint8_t remote_ddr_size;
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} __packed;
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/*
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* N1SDP platform supports RDIMMs with ECC capability. To use the ECC
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* capability, the entire DDR memory space has to be zeroed out before
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* enabling the ECC bits in DMC620. Zeroing out several gigabytes of
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* memory from SCP is quite time consuming so the following function
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* is added to zero out the DDR memory from application processor which is
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* much faster compared to SCP.
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*/
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void dmc_ecc_setup(uint8_t ddr_size_gb)
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{
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uint64_t dram2_size;
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dram2_size = (ddr_size_gb * 1024UL * 1024UL * 1024UL) -
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ARM_DRAM1_SIZE;
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INFO("Zeroing DDR memories\n");
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zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size);
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flush_dcache_range(ARM_DRAM2_BASE, dram2_size);
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INFO("Enabling ECC on DMCs\n");
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/* Set DMCs to CONFIG state before writing ERR0CTLR0 register */
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mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
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mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG);
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/* Enable ECC in DMCs */
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mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
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mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN);
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/* Set DMCs to READY state */
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mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
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mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
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}
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void bl2_platform_setup(void)
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{
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int ret;
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struct n1sdp_plat_info plat_info;
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ret = sds_init();
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if (ret != SDS_OK) {
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ERROR("SDS initialization failed\n");
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panic();
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}
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ret = sds_struct_read(N1SDP_SDS_PLATFORM_INFO_STRUCT_ID,
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N1SDP_SDS_PLATFORM_INFO_OFFSET,
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&plat_info,
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N1SDP_SDS_PLATFORM_INFO_SIZE,
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SDS_ACCESS_MODE_NON_CACHED);
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if (ret != SDS_OK) {
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ERROR("Error getting platform info from SDS\n");
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panic();
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}
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/* Validate plat_info SDS */
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if ((plat_info.local_ddr_size == 0)
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|| (plat_info.local_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB)
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|| (plat_info.remote_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB)
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|| (plat_info.secondary_count > N1SDP_MAX_SECONDARY_COUNT)) {
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ERROR("platform info SDS is corrupted\n");
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panic();
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}
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dmc_ecc_setup(plat_info.local_ddr_size);
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arm_bl2_platform_setup();
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}
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