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131 lines
3.7 KiB
131 lines
3.7 KiB
/*
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* Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <context.h>
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#include <common/debug.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <plat/common/platform.h>
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#include "../bl1_private.h"
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/* Following contains the cpu context pointers. */
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static void *bl1_cpu_context_ptr[2];
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entry_point_info_t *bl2_ep_info;
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void *cm_get_context(uint32_t security_state)
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{
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assert(sec_state_is_valid(security_state));
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return bl1_cpu_context_ptr[security_state];
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}
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void cm_set_context(void *context, uint32_t security_state)
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{
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assert(sec_state_is_valid(security_state));
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bl1_cpu_context_ptr[security_state] = context;
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}
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#if ENABLE_RME
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/*******************************************************************************
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* This function prepares the entry point information to run BL2 in Root world,
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* i.e. EL3, for the case when FEAT_RME is enabled.
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******************************************************************************/
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void bl1_prepare_next_image(unsigned int image_id)
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{
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image_desc_t *bl2_desc;
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assert(image_id == BL2_IMAGE_ID);
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/* Get the image descriptor. */
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bl2_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
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assert(bl2_desc != NULL);
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/* Get the entry point info. */
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bl2_ep_info = &bl2_desc->ep_info;
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bl2_ep_info->spsr = (uint32_t)SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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/*
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* Flush cache since bl2_ep_info is accessed after MMU is disabled
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* before jumping to BL2.
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*/
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flush_dcache_range((uintptr_t)bl2_ep_info, sizeof(entry_point_info_t));
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/* Indicate that image is in execution state. */
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bl2_desc->state = IMAGE_STATE_EXECUTED;
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/* Print debug info and flush the console before running BL2. */
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print_entry_point_info(bl2_ep_info);
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}
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#else
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/*******************************************************************************
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* This function prepares the context for Secure/Normal world images.
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* Normal world images are transitioned to EL2(if supported) else EL1.
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******************************************************************************/
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void bl1_prepare_next_image(unsigned int image_id)
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{
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/*
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* Following array will be used for context management.
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* There are 2 instances, for the Secure and Non-Secure contexts.
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*/
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static cpu_context_t bl1_cpu_context[2];
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unsigned int security_state, mode = MODE_EL1;
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image_desc_t *desc;
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entry_point_info_t *next_bl_ep;
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#if CTX_INCLUDE_AARCH32_REGS
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/*
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* Ensure that the build flag to save AArch32 system registers in CPU
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* context is not set for AArch64-only platforms.
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*/
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if (el_implemented(1) == EL_IMPL_A64ONLY) {
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ERROR("EL1 supports AArch64-only. Please set build flag "
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"CTX_INCLUDE_AARCH32_REGS = 0\n");
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panic();
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}
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#endif
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/* Get the image descriptor. */
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desc = bl1_plat_get_image_desc(image_id);
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assert(desc != NULL);
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/* Get the entry point info. */
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next_bl_ep = &desc->ep_info;
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/* Get the image security state. */
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security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
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/* Setup the Secure/Non-Secure context if not done already. */
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if (cm_get_context(security_state) == NULL)
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cm_set_context(&bl1_cpu_context[security_state], security_state);
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/* Prepare the SPSR for the next BL image. */
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if ((security_state != SECURE) && (el_implemented(2) != EL_IMPL_NONE)) {
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mode = MODE_EL2;
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}
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next_bl_ep->spsr = (uint32_t)SPSR_64((uint64_t) mode,
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(uint64_t)MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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/* Allow platform to make change */
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bl1_plat_set_ep_info(image_id, next_bl_ep);
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/* Prepare the context for the next BL image. */
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cm_init_my_context(next_bl_ep);
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cm_prepare_el3_exit(security_state);
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/* Indicate that image is in execution state. */
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desc->state = IMAGE_STATE_EXECUTED;
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print_entry_point_info(next_bl_ep);
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}
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#endif /* ENABLE_RME */
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