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86 lines
2.2 KiB
86 lines
2.2 KiB
Intel Agilex SoCFPGA
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Agilex SoCFPGA is a FPGA with integrated quad-core 64-bit Arm Cortex A53 processor.
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Upon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializes
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the hardware, then loads bl31 and bl33 (UEFI) into DDR and boots to bl33.
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::
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Boot ROM --> Trusted Firmware-A --> UEFI
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How to build
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------------
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Code Locations
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~~~~~~~~~~~~~~
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- Trusted Firmware-A:
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`link <https://github.com/ARM-software/arm-trusted-firmware>`__
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- UEFI (to be updated with new upstreamed UEFI):
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`link <https://github.com/altera-opensource/uefi-socfpga>`__
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Build Procedure
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~~~~~~~~~~~~~~~
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- Fetch all the above 2 repositories into local host.
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Make all the repositories in the same ${BUILD\_PATH}.
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- Prepare the AARCH64 toolchain.
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- Build UEFI using Agilex platform as configuration
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This will be updated to use an updated UEFI using the latest EDK2 source
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.. code:: bash
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make CROSS_COMPILE=aarch64-linux-gnu- device=agx
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- Build atf providing the previously generated UEFI as the BL33 image
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.. code:: bash
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make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=agilex
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BL33=PEI.ROM
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Install Procedure
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~~~~~~~~~~~~~~~~~
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- dd fip.bin to a A2 partition on the MMC drive to be booted in Agilex
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board.
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- Generate a SOF containing bl2
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.. code:: bash
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aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
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quartus_cpf --bootloader bl2.hex <quartus_generated_sof> <output_sof_with_bl2>
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- Configure SOF to board
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.. code:: bash
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nios2-configure-sof <output_sof_with_bl2>
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Boot trace
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----------
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::
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INFO: DDR: DRAM calibration success.
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INFO: ECC is disabled.
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NOTICE: BL2: v2.1(debug)
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NOTICE: BL2: Built
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INFO: BL2: Doing platform setup
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NOTICE: BL2: Booting BL31
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INFO: Entry point address = 0xffe1c000
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INFO: SPSR = 0x3cd
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NOTICE: BL31: v2.1(debug)
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NOTICE: BL31: Built
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INFO: ARM GICv2 driver initialized
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INFO: BL31: Initializing runtime services
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WARNING: BL31: cortex_a53
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INFO: BL31: Preparing for EL3 exit to normal world
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INFO: Entry point address = 0x50000
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INFO: SPSR = 0x3c9
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