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57 lines
2.3 KiB
57 lines
2.3 KiB
#
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# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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#
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# Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# Neither the name of ARM nor the names of its contributors may be used
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# to endorse or promote products derived from this software without specific
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# prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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TEGRA_BOOT_UART_BASE := 0x70006000
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$(eval $(call add_define,TEGRA_BOOT_UART_BASE))
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TZDRAM_BASE := 0xFDC00000
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$(eval $(call add_define,TZDRAM_BASE))
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ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1
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$(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT))
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ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1
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$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS))
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PLATFORM_CLUSTER_COUNT := 2
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$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
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PLATFORM_MAX_CPUS_PER_CLUSTER := 4
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$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
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BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a57.S \
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${SOC_DIR}/plat_psci_handlers.c \
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${SOC_DIR}/plat_setup.c \
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${SOC_DIR}/plat_secondary.c
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# Enable workarounds for selected Cortex-A53 erratas.
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ERRATA_A53_826319 := 1
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