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158 lines
3.2 KiB
158 lines
3.2 KiB
/*
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* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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model = "A5DS";
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compatible = "arm,A5DS";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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cpu_on = <0x84000003>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "psci";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <2>;
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next-level-cache = <&L2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <3>;
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next-level-cache = <&L2>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x7F000000>;
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};
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L2: cache-controller@1C010000 {
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compatible = "arm,pl310-cache";
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reg = <0x1C010000 0x1000>;
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interrupts = <0 84 4>;
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cache-level = <2>;
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cache-unified;
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arm,data-latency = <1 1 1>;
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arm,tag-latency = <1 1 1>;
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};
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refclk7500khz: refclk7500khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <7500000>;
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clock-output-names = "apb_pclk";
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};
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refclk24mhz: refclk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "apb_pclk";
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};
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smbclk: refclk24mhzx2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-output-names = "smclk";
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};
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rtc@1a220000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x1a220000 0x1000>;
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clocks = <&refclk24mhz>;
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interrupts = <0 6 0xf04>;
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clock-names = "apb_pclk";
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};
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gic: interrupt-controller@1c001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1c001000 0x1000>,
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<0x1c000100 0x100>;
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interrupts = <1 9 0xf04>;
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};
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serial0: uart@1a200000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1a200000 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 8 0xf04>;
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clocks = <&refclk7500khz>;
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clock-names = "apb_pclk";
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};
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serial1: uart@1a210000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1a210000 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 9 0xf04>;
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clocks = <&refclk7500khz>;
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clock-names = "apb_pclk";
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};
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timer0: timer@1a040000 {
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compatible = "arm,armv7-timer-mem";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = <0x1a040000 0x1000>;
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clock-frequency = <7500000>;
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frame@1a050000 {
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frame-number = <0>;
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interrupts = <0 2 0xf04>;
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reg = <0x1a050000 0x1000>;
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};
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};
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v2m_fixed_3v3: fixed-regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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ethernet@4020000 {
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compatible = "smsc,lan9220", "smsc,lan9115";
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reg = <0x40200000 0x10000>;
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interrupt-parent = <&gic>;
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interrupts = <0 43 0xf04>;
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reg-io-width = <4>;
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phy-mode = "mii";
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smsc,irq-active-high;
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vdd33a-supply = <&v2m_fixed_3v3>;
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vddvario-supply = <&v2m_fixed_3v3>;
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};
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};
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