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92 lines
1.8 KiB
92 lines
1.8 KiB
// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
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/*
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* Copyright (c) 2019-2020, Arm Limited.
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*/
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/dts-v1/;
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#include "n1sdp.dtsi"
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/ {
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model = "Arm Neoverse N1 System Development Platform";
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compatible = "arm,neoverse-n1-sdp", "arm,neoverse-n1-soc";
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aliases {
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serial0 = &soc_uart0;
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};
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chosen {
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stdout-path = "soc_uart0:115200n8";
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};
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/* This configuration assumes that standard setup with two DIMM modules.
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* In the first 2GB of DRAM bank the top 16MB are reserved by firmware as secure memory.
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* This configuration assumes 16GB of total DRAM being populated.
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*/
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x0 0x7f000000>,
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<0x00000080 0x80000000 0x3 0x80000000>;
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numa-node-id = <0>;
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};
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soc_refclk60mhz: refclk60mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <60000000>;
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clock-output-names = "iofpga_clk";
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};
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soc_hdlcdclk: hdlcdclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <23750000>;
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clock-output-names = "hdlcdclk";
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};
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hdlcd: hdlcd@1c050000 {
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compatible = "arm,hdlcd";
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reg = <0 0x1c050000 0 0x1000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_hdlcdclk>;
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clock-names = "pxlclk";
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port {
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hdlcd0_output: endpoint {
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remote-endpoint = <&tda998x_0_input>;
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};
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};
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};
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i2c@1c0f0000 {
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compatible = "arm,versatile-i2c";
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reg = <0x0 0x1c0f0000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <400000>;
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i2c-sda-hold-time-ns = <500>;
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clocks = <&soc_refclk60mhz>;
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hdmi-transmitter@70 {
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compatible = "nxp,tda998x";
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reg = <0x70>;
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port {
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tda998x_0_input: endpoint {
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remote-endpoint = <&hdlcd0_output>;
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};
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};
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};
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};
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};
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&pcie_ctlr {
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status = "okay";
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};
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&ccix_pcie_ctlr {
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status = "okay";
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};
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&soc_uart0 {
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status = "okay";
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};
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