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92 lines
2.1 KiB
92 lines
2.1 KiB
/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <libfdt.h>
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv2.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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struct stm32_gic_instance {
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uint32_t cells;
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uint32_t phandle_node;
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};
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/******************************************************************************
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* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
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* interrupts.
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*****************************************************************************/
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static const interrupt_prop_t stm32mp1_interrupt_props[] = {
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PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
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PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
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};
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/* Fix target_mask_array as secondary core is not able to initialize it */
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static unsigned int target_mask_array[PLATFORM_CORE_COUNT] = {1, 2};
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static gicv2_driver_data_t platform_gic_data = {
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.interrupt_props = stm32mp1_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(stm32mp1_interrupt_props),
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.target_masks = target_mask_array,
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.target_masks_num = ARRAY_SIZE(target_mask_array),
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};
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static struct stm32_gic_instance stm32_gic;
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void stm32mp1_gic_init(void)
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{
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int node;
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void *fdt;
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const fdt32_t *cuint;
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struct dt_node_info dt_gic;
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if (fdt_get_address(&fdt) == 0) {
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panic();
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}
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node = dt_get_node(&dt_gic, -1, "arm,cortex-a7-gic");
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if (node < 0) {
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panic();
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}
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platform_gic_data.gicd_base = dt_gic.base;
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cuint = fdt_getprop(fdt, node, "reg", NULL);
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if (cuint == NULL) {
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panic();
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}
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platform_gic_data.gicc_base = fdt32_to_cpu(*(cuint + 2));
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cuint = fdt_getprop(fdt, node, "#interrupt-cells", NULL);
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if (cuint == NULL) {
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panic();
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}
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stm32_gic.cells = fdt32_to_cpu(*cuint);
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stm32_gic.phandle_node = fdt_get_phandle(fdt, node);
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if (stm32_gic.phandle_node == 0U) {
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panic();
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}
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gicv2_driver_init(&platform_gic_data);
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gicv2_distif_init();
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stm32mp1_gic_pcpu_init();
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}
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void stm32mp1_gic_pcpu_init(void)
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{
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gicv2_pcpu_distif_init();
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gicv2_set_pe_target_mask(plat_my_core_pos());
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gicv2_cpuif_enable();
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}
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