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548 lines
14 KiB
548 lines
14 KiB
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef UFS_H
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#define UFS_H
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#include <lib/utils_def.h>
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/* register map of UFSHCI */
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/* Controller Capabilities */
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#define CAP 0x00
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#define CAP_NUTRS_MASK 0x1F
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/* UFS Version */
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#define VER 0x08
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/* Host Controller Identification - Product ID */
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#define HCDDID 0x10
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/* Host Controller Identification Descriptor - Manufacturer ID */
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#define HCPMID 0x14
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/* Auto-Hibernate Idle Timer */
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#define AHIT 0x18
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/* Interrupt Status */
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#define IS 0x20
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/* Interrupt Enable */
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#define IE 0x24
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/* System Bus Fatal Error Status */
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#define UFS_INT_SBFES (1 << 17)
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/* Host Controller Fatal Error Status */
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#define UFS_INT_HCFES (1 << 16)
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/* UTP Error Status */
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#define UFS_INT_UTPES (1 << 12)
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/* Device Fatal Error Status */
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#define UFS_INT_DFES (1 << 11)
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/* UIC Command Completion Status */
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#define UFS_INT_UCCS (1 << 10)
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/* UTP Task Management Request Completion Status */
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#define UFS_INT_UTMRCS (1 << 9)
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/* UIC Link Startup Status */
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#define UFS_INT_ULSS (1 << 8)
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/* UIC Link Lost Status */
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#define UFS_INT_ULLS (1 << 7)
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/* UIC Hibernate Enter Status */
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#define UFS_INT_UHES (1 << 6)
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/* UIC Hibernate Exit Status */
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#define UFS_INT_UHXS (1 << 5)
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/* UIC Power Mode Status */
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#define UFS_INT_UPMS (1 << 4)
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/* UIC Test Mode Status */
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#define UFS_INT_UTMS (1 << 3)
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/* UIC Error */
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#define UFS_INT_UE (1 << 2)
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/* UIC DME_ENDPOINTRESET Indication */
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#define UFS_INT_UDEPRI (1 << 1)
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/* UTP Transfer Request Completion Status */
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#define UFS_INT_UTRCS (1 << 0)
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/* Host Controller Status */
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#define HCS 0x30
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#define HCS_UPMCRS_MASK (7 << 8)
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#define HCS_PWR_LOCAL (1 << 8)
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#define HCS_UCRDY (1 << 3)
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#define HCS_UTMRLRDY (1 << 2)
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#define HCS_UTRLRDY (1 << 1)
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#define HCS_DP (1 << 0)
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/* Host Controller Enable */
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#define HCE 0x34
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#define HCE_ENABLE 1
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/* Host UIC Error Code PHY Adapter Layer */
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#define UECPA 0x38
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/* Host UIC Error Code Data Link Layer */
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#define UECDL 0x3C
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/* Host UIC Error Code Network Layer */
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#define UECN 0x40
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/* Host UIC Error Code Transport Layer */
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#define UECT 0x44
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/* Host UIC Error Code */
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#define UECDME 0x48
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/* UTP Transfer Request Interrupt Aggregation Control Register */
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#define UTRIACR 0x4C
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#define UTRIACR_IAEN (1U << 31)
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#define UTRIACR_IAPWEN (1 << 24)
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#define UTRIACR_IASB (1 << 20)
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#define UTRIACR_CTR (1 << 16)
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#define UTRIACR_IACTH(x) (((x) & 0x1F) << 8)
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#define UTRIACR_IATOVAL(x) ((x) & 0xFF)
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/* UTP Transfer Request List Base Address */
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#define UTRLBA 0x50
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/* UTP Transfer Request List Base Address Upper 32-bits */
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#define UTRLBAU 0x54
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/* UTP Transfer Request List Door Bell Register */
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#define UTRLDBR 0x58
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/* UTP Transfer Request List Clear Register */
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#define UTRLCLR 0x5C
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/* UTP Transfer Request List Run Stop Register */
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#define UTRLRSR 0x60
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#define UTMRLBA 0x70
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#define UTMRLBAU 0x74
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#define UTMRLDBR 0x78
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#define UTMRLCLR 0x7C
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#define UTMRLRSR 0x80
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/* UIC Command */
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#define UICCMD 0x90
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/* UIC Command Argument 1 */
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#define UCMDARG1 0x94
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/* UIC Command Argument 2 */
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#define UCMDARG2 0x98
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/* UIC Command Argument 3 */
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#define UCMDARG3 0x9C
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#define UFS_BLOCK_SHIFT 12 /* 4KB */
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#define UFS_BLOCK_SIZE (1 << UFS_BLOCK_SHIFT)
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#define UFS_BLOCK_MASK (UFS_BLOCK_SIZE - 1)
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#define UFS_MAX_LUNS 8
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/* UTP Transfer Request Descriptor */
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/* Command Type */
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#define CT_UFS_STORAGE 1
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#define CT_SCSI 0
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/* Data Direction */
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#define DD_OUT 2 /* Device --> Host */
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#define DD_IN 1 /* Host --> Device */
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#define DD_NO_DATA_TRANSFER 0
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#define UTP_TRD_SIZE 32
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/* Transaction Type */
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#define TRANS_TYPE_HD (1 << 7) /* E2ECRC */
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#define TRANS_TYPE_DD (1 << 6)
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#define TRANS_TYPE_CODE_MASK 0x3F
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#define QUERY_RESPONSE_UPIU (0x36 << 0)
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#define READY_TO_TRANSACTION_UPIU (0x31 << 0)
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#define DATA_IN_UPIU (0x22 << 0)
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#define RESPONSE_UPIU (0x21 << 0)
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#define NOP_IN_UPIU (0x20 << 0)
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#define QUERY_REQUEST_UPIU (0x16 << 0)
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#define DATA_OUT_UPIU (0x02 << 0)
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#define CMD_UPIU (0x01 << 0)
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#define NOP_OUT_UPIU (0x00 << 0)
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#define OCS_SUCCESS 0x0
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#define OCS_INVALID_FUNC_ATTRIBUTE 0x1
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#define OCS_MISMATCH_REQUEST_SIZE 0x2
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#define OCS_MISMATCH_RESPONSE_SIZE 0x3
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#define OCS_PEER_COMMUNICATION_FAILURE 0x4
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#define OCS_ABORTED 0x5
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#define OCS_FATAL_ERROR 0x6
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#define OCS_MASK 0xF
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/* UIC Command */
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#define DME_GET 0x01
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#define DME_SET 0x02
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#define DME_PEER_GET 0x03
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#define DME_PEER_SET 0x04
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#define DME_POWERON 0x10
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#define DME_POWEROFF 0x11
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#define DME_ENABLE 0x12
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#define DME_RESET 0x14
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#define DME_ENDPOINTRESET 0x15
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#define DME_LINKSTARTUP 0x16
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#define DME_HIBERNATE_ENTER 0x17
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#define DME_HIBERNATE_EXIT 0x18
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#define DME_TEST_MODE 0x1A
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#define GEN_SELECTOR_IDX(x) ((x) & 0xFFFF)
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#define CONFIG_RESULT_CODE_MASK 0xFF
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#define CDBCMD_TEST_UNIT_READY 0x00
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#define CDBCMD_READ_6 0x08
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#define CDBCMD_WRITE_6 0x0A
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#define CDBCMD_START_STOP_UNIT 0x1B
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#define CDBCMD_READ_CAPACITY_10 0x25
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#define CDBCMD_READ_10 0x28
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#define CDBCMD_WRITE_10 0x2A
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#define CDBCMD_READ_16 0x88
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#define CDBCMD_WRITE_16 0x8A
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#define CDBCMD_READ_CAPACITY_16 0x9E
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#define CDBCMD_REPORT_LUNS 0xA0
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#define UPIU_FLAGS_R (1 << 6)
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#define UPIU_FLAGS_W (1 << 5)
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#define UPIU_FLAGS_ATTR_MASK (3 << 0)
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#define UPIU_FLAGS_ATTR_S (0 << 0) /* Simple */
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#define UPIU_FLAGS_ATTR_O (1 << 0) /* Ordered */
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#define UPIU_FLAGS_ATTR_HQ (2 << 0) /* Head of Queue */
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#define UPIU_FLAGS_ATTR_ACA (3 << 0)
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#define UPIU_FLAGS_O (1 << 6)
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#define UPIU_FLAGS_U (1 << 5)
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#define UPIU_FLAGS_D (1 << 4)
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#define QUERY_FUNC_STD_READ 0x01
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#define QUERY_FUNC_STD_WRITE 0x81
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#define QUERY_NOP 0x00
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#define QUERY_READ_DESC 0x01
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#define QUERY_WRITE_DESC 0x02
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#define QUERY_READ_ATTR 0x03
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#define QUERY_WRITE_ATTR 0x04
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#define QUERY_READ_FLAG 0x05
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#define QUERY_SET_FLAG 0x06
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#define QUERY_CLEAR_FLAG 0x07
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#define QUERY_TOGGLE_FLAG 0x08
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#define RW_WITHOUT_CACHE 0x18
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#define DESC_TYPE_DEVICE 0x00
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#define DESC_TYPE_CONFIGURATION 0x01
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#define DESC_TYPE_UNIT 0x02
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#define DESC_TYPE_INTERCONNECT 0x04
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#define DESC_TYPE_STRING 0x05
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#define DESC_DEVICE_MAX_SIZE 0x1F
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#define DEVICE_DESC_PARAM_MANF_ID 0x18
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#define ATTR_CUR_PWR_MODE 0x02 /* bCurrentPowerMode */
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#define ATTR_ACTIVECC 0x03 /* bActiveICCLevel */
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#define DEVICE_DESCRIPTOR_LEN 0x40
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#define UNIT_DESCRIPTOR_LEN 0x23
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#define QUERY_RESP_SUCCESS 0x00
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#define QUERY_RESP_OPCODE 0xFE
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#define QUERY_RESP_GENERAL_FAIL 0xFF
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#define SENSE_KEY_NO_SENSE 0x00
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#define SENSE_KEY_RECOVERED_ERROR 0x01
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#define SENSE_KEY_NOT_READY 0x02
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#define SENSE_KEY_MEDIUM_ERROR 0x03
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#define SENSE_KEY_HARDWARE_ERROR 0x04
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#define SENSE_KEY_ILLEGAL_REQUEST 0x05
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#define SENSE_KEY_UNIT_ATTENTION 0x06
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#define SENSE_KEY_DATA_PROTECT 0x07
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#define SENSE_KEY_BLANK_CHECK 0x08
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#define SENSE_KEY_VENDOR_SPECIFIC 0x09
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#define SENSE_KEY_COPY_ABORTED 0x0A
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#define SENSE_KEY_ABORTED_COMMAND 0x0B
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#define SENSE_KEY_VOLUME_OVERFLOW 0x0D
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#define SENSE_KEY_MISCOMPARE 0x0E
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#define SENSE_DATA_VALID 0x70
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#define SENSE_DATA_LENGTH 18
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#define READ_CAPACITY_LENGTH 8
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#define FLAG_DEVICE_INIT 0x01
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#define UFS_VENDOR_SKHYNIX U(0x1AD)
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#define MAX_MODEL_LEN 16
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/**
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* ufs_dev_desc - ufs device details from the device descriptor
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* @wmanufacturerid: card details
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* @model: card model
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*/
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struct ufs_dev_desc {
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uint16_t wmanufacturerid;
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int8_t model[MAX_MODEL_LEN + 1];
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};
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/* UFS Driver Flags */
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#define UFS_FLAGS_SKIPINIT (1 << 0)
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#define UFS_FLAGS_VENDOR_SKHYNIX (U(1) << 2)
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typedef struct sense_data {
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uint8_t resp_code : 7;
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uint8_t valid : 1;
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uint8_t reserved0;
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uint8_t sense_key : 4;
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uint8_t reserved1 : 1;
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uint8_t ili : 1;
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uint8_t eom : 1;
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uint8_t file_mark : 1;
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uint8_t info[4];
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uint8_t asl;
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uint8_t cmd_spec_len[4];
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uint8_t asc;
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uint8_t ascq;
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uint8_t fruc;
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uint8_t sense_key_spec0 : 7;
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uint8_t sksv : 1;
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uint8_t sense_key_spec1;
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uint8_t sense_key_spec2;
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} sense_data_t;
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/* UTP Transfer Request Descriptor */
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typedef struct utrd_header {
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uint32_t reserved0 : 24;
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uint32_t i : 1; /* interrupt */
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uint32_t dd : 2; /* data direction */
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uint32_t reserved1 : 1;
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uint32_t ct : 4; /* command type */
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uint32_t reserved2;
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uint32_t ocs : 8; /* Overall Command Status */
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uint32_t reserved3 : 24;
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uint32_t reserved4;
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uint32_t ucdba; /* aligned to 128-byte */
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uint32_t ucdbau; /* Upper 32-bits */
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uint32_t rul : 16; /* Response UPIU Length */
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uint32_t ruo : 16; /* Response UPIU Offset */
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uint32_t prdtl : 16; /* PRDT Length */
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uint32_t prdto : 16; /* PRDT Offset */
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} utrd_header_t; /* 8 words with little endian */
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/* UTP Task Management Request Descriptor */
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typedef struct utp_utmrd {
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/* 4 words with little endian */
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uint32_t reserved0 : 24;
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uint32_t i : 1; /* interrupt */
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uint32_t reserved1 : 7;
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uint32_t reserved2;
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uint32_t ocs : 8; /* Overall Command Status */
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uint32_t reserved3 : 24;
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uint32_t reserved4;
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/* followed by 8 words UPIU with big endian */
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/* followed by 8 words Response UPIU with big endian */
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} utp_utmrd_t;
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/* NOP OUT UPIU */
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typedef struct nop_out_upiu {
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uint8_t trans_type;
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uint8_t flags;
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uint8_t reserved0;
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uint8_t task_tag;
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uint8_t reserved1;
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uint8_t reserved2;
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uint8_t reserved3;
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uint8_t reserved4;
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uint8_t total_ehs_len;
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uint8_t reserved5;
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uint16_t data_segment_len;
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uint32_t reserved6;
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uint32_t reserved7;
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uint32_t reserved8;
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uint32_t reserved9;
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uint32_t reserved10;
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uint32_t e2ecrc;
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} nop_out_upiu_t; /* 36 bytes with big endian */
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/* NOP IN UPIU */
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typedef struct nop_in_upiu {
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uint8_t trans_type;
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uint8_t flags;
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uint8_t reserved0;
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uint8_t task_tag;
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uint8_t reserved1;
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uint8_t reserved2;
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uint8_t response;
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uint8_t reserved3;
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uint8_t total_ehs_len;
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uint8_t dev_info;
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uint16_t data_segment_len;
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uint32_t reserved4;
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uint32_t reserved5;
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uint32_t reserved6;
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uint32_t reserved7;
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uint32_t reserved8;
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uint32_t e2ecrc;
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} nop_in_upiu_t; /* 36 bytes with big endian */
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/* Command UPIU */
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typedef struct cmd_upiu {
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uint8_t trans_type;
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uint8_t flags;
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uint8_t lun;
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uint8_t task_tag;
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uint8_t cmd_set_type;
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uint8_t reserved0;
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uint8_t reserved1;
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uint8_t reserved2;
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uint8_t total_ehs_len;
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uint8_t reserved3;
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uint16_t data_segment_len;
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uint32_t exp_data_trans_len;
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/*
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* A CDB has a fixed length of 16bytes or a variable length
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* of between 12 and 260 bytes
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*/
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uint8_t cdb[16]; /* little endian */
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} cmd_upiu_t; /* 32 bytes with big endian except for cdb[] */
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typedef struct query_desc {
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uint8_t opcode;
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uint8_t idn;
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uint8_t index;
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uint8_t selector;
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uint8_t reserved0[2];
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uint16_t length;
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uint32_t reserved2[2];
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} query_desc_t; /* 16 bytes with big endian */
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typedef struct query_flag {
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uint8_t opcode;
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uint8_t idn;
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uint8_t index;
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uint8_t selector;
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uint8_t reserved0[7];
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uint8_t value;
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uint32_t reserved8;
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} query_flag_t; /* 16 bytes with big endian */
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typedef struct query_attr {
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uint8_t opcode;
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uint8_t idn;
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uint8_t index;
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uint8_t selector;
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uint8_t reserved0[4];
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uint32_t value; /* little endian */
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uint32_t reserved4;
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} query_attr_t; /* 16 bytes with big endian except for value */
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/* Query Request UPIU */
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typedef struct query_upiu {
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uint8_t trans_type;
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uint8_t flags;
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uint8_t reserved0;
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uint8_t task_tag;
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uint8_t reserved1;
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uint8_t query_func;
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uint8_t reserved2;
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uint8_t reserved3;
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uint8_t total_ehs_len;
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uint8_t reserved4;
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uint16_t data_segment_len;
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/* Transaction Specific Fields */
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union {
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query_desc_t desc;
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query_flag_t flag;
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query_attr_t attr;
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} ts;
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uint32_t reserved5;
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} query_upiu_t; /* 32 bytes with big endian */
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/* Query Response UPIU */
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typedef struct query_resp_upiu {
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uint8_t trans_type;
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uint8_t flags;
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uint8_t reserved0;
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uint8_t task_tag;
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uint8_t reserved1;
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uint8_t query_func;
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uint8_t query_resp;
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uint8_t reserved2;
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uint8_t total_ehs_len;
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uint8_t dev_info;
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uint16_t data_segment_len;
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union {
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query_desc_t desc;
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query_flag_t flag;
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query_attr_t attr;
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} ts;
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uint32_t reserved3;
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} query_resp_upiu_t; /* 32 bytes with big endian */
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/* Response UPIU */
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typedef struct resp_upiu {
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uint8_t trans_type;
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uint8_t flags;
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uint8_t lun;
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uint8_t task_tag;
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uint8_t cmd_set_type;
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uint8_t reserved0;
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uint8_t reserved1;
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uint8_t status;
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uint8_t total_ehs_len;
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uint8_t dev_info;
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uint16_t data_segment_len;
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uint32_t res_trans_cnt; /* Residual Transfer Count */
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uint32_t reserved2[4];
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uint16_t sense_data_len;
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union {
|
|
uint8_t sense_data[18];
|
|
sense_data_t sense;
|
|
} sd;
|
|
} resp_upiu_t; /* 52 bytes with big endian */
|
|
|
|
typedef struct cmd_info {
|
|
uintptr_t buf;
|
|
size_t length;
|
|
int lba;
|
|
uint8_t op;
|
|
uint8_t direction;
|
|
uint8_t lun;
|
|
} cmd_info_t;
|
|
|
|
typedef struct utp_utrd {
|
|
uintptr_t header; /* utrd_header_t */
|
|
uintptr_t upiu;
|
|
uintptr_t resp_upiu;
|
|
uintptr_t prdt;
|
|
size_t size_upiu;
|
|
size_t size_resp_upiu;
|
|
size_t size_prdt;
|
|
int task_tag;
|
|
} utp_utrd_t;
|
|
|
|
/* Physical Region Description Table */
|
|
typedef struct prdt {
|
|
uint32_t dba; /* Data Base Address */
|
|
uint32_t dbau; /* Data Base Address Upper 32-bits */
|
|
uint32_t reserved0;
|
|
uint32_t dbc : 18; /* Data Byte Count */
|
|
uint32_t reserved1 : 14;
|
|
} prdt_t;
|
|
|
|
typedef struct uic_cmd {
|
|
uint32_t op;
|
|
uint32_t arg1;
|
|
uint32_t arg2;
|
|
uint32_t arg3;
|
|
} uic_cmd_t;
|
|
|
|
typedef struct ufs_params {
|
|
uintptr_t reg_base;
|
|
uintptr_t desc_base;
|
|
size_t desc_size;
|
|
unsigned long flags;
|
|
} ufs_params_t;
|
|
|
|
typedef struct ufs_ops {
|
|
int (*phy_init)(ufs_params_t *params);
|
|
int (*phy_set_pwr_mode)(ufs_params_t *params);
|
|
} ufs_ops_t;
|
|
|
|
int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd);
|
|
int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val);
|
|
int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val);
|
|
|
|
unsigned int ufs_read_attr(int idn);
|
|
void ufs_write_attr(int idn, unsigned int value);
|
|
unsigned int ufs_read_flag(int idn);
|
|
void ufs_set_flag(int idn);
|
|
void ufs_clear_flag(int idn);
|
|
void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size);
|
|
void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size);
|
|
size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size);
|
|
size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size);
|
|
int ufs_init(const ufs_ops_t *ops, ufs_params_t *params);
|
|
|
|
#endif /* UFS_H */
|
|
|