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75 lines
2.7 KiB
75 lines
2.7 KiB
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <lib/utils_def.h>
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#include <tegra_def.h>
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/*
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* Platform binary types for linking
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*/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#ifdef IMAGE_BL31
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#define PLATFORM_STACK_SIZE U(0x400)
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#endif
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#define TEGRA_PRIMARY_CPU U(0x0)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_MAX_CPUS_PER_CLUSTER)
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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PLATFORM_CLUSTER_COUNT + 1)
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/*******************************************************************************
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* Platform console related constants
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******************************************************************************/
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#define TEGRA_CONSOLE_BAUDRATE U(115200)
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#define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000)
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#define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000)
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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/* Size of trusted dram */
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#define TZDRAM_SIZE U(0x00400000)
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#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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#define BL31_SIZE U(0x40000)
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#define BL31_BASE TZDRAM_BASE
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#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
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#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
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#define BL32_LIMIT TZDRAM_END
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/*******************************************************************************
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */
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/*******************************************************************************
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* Dummy macros to compile io_storage support
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******************************************************************************/
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#define MAX_IO_DEVICES U(0)
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#define MAX_IO_HANDLES U(0)
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#endif /* PLATFORM_DEF_H */
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