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105 lines
4.6 KiB
105 lines
4.6 KiB
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PL011_H__
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#define __PL011_H__
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/* PL011 Registers */
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#define UARTDR 0x000
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#define UARTRSR 0x004
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#define UARTECR 0x004
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#define UARTFR 0x018
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#define UARTIMSC 0x038
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#define UARTRIS 0x03C
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#define UARTICR 0x044
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/* PL011 registers (out of the SBSA specification) */
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#if !PL011_GENERIC_UART
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#define UARTILPR 0x020
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#define UARTIBRD 0x024
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#define UARTFBRD 0x028
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#define UARTLCR_H 0x02C
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#define UARTCR 0x030
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#define UARTIFLS 0x034
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#define UARTMIS 0x040
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#define UARTDMACR 0x048
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#endif /* !PL011_GENERIC_UART */
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/* Data status bits */
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#define UART_DATA_ERROR_MASK 0x0F00
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/* Status reg bits */
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#define UART_STATUS_ERROR_MASK 0x0F
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/* Flag reg bits */
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#define PL011_UARTFR_RI (1 << 8) /* Ring indicator */
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#define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */
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#define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */
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#define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */
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#define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */
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#define PL011_UARTFR_BUSY (1 << 3) /* UART busy */
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#define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */
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#define PL011_UARTFR_DSR (1 << 1) /* Data set ready */
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#define PL011_UARTFR_CTS (1 << 0) /* Clear to send */
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#define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in UARTFR register */
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#define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */
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/* Control reg bits */
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#if !PL011_GENERIC_UART
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#define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */
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#define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */
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#define PL011_UARTCR_RTS (1 << 11) /* Request to send */
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#define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */
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#define PL011_UARTCR_RXE (1 << 9) /* Receive enable */
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#define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */
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#define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */
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#define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */
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#if !defined(PL011_LINE_CONTROL)
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/* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */
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#define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8)
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#endif
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/* Line Control Register Bits */
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#define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */
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#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
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#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
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#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
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#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
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#define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */
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#define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */
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#define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */
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#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */
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#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */
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#endif /* !PL011_GENERIC_UART */
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#endif /* __PL011_H__ */
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