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74 lines
2.1 KiB
74 lines
2.1 KiB
/*
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* Copyright (c) 2016 - 2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PAXB_H
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#define PAXB_H
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/* total number of PCIe cores */
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#define NUM_OF_SR_PCIE_CORES 8
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#define NUM_OF_NS3Z_PCIE_CORES 1
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/*
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* List of PCIe core and PAXB wrapper memory power registers
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*/
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#define PCIE_CORE_BASE 0x40000800
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#define PCIE_CORE_SOFT_RST_CFG_BASE (PCIE_CORE_BASE + 0x40)
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#define PCIE_CORE_SOFT_RST 0x1
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#define PCIE_CORE_ISO_CFG_BASE (PCIE_CORE_BASE + 0x54)
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#define PCIE_CORE_MEM_ISO 0x2
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#define PCIE_CORE_ISO 0x1
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#define PCIE_CORE_MEM_PWR_BASE (PCIE_CORE_BASE + 0x58)
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#define PCIE_PAXB_MEM_PWR_BASE (PCIE_CORE_BASE + 0x5c)
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#define PCIE_CORE_PMI_CFG_BASE (PCIE_CORE_BASE + 0x64)
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#define PCIE_CORE_RESERVED_CFG (PCIE_CORE_BASE + 0x6c)
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#define PCIE_CORE_MEM_PWR_STATUS_BASE (PCIE_CORE_BASE + 0x74)
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#define PCIE_PAXB_MEM_PWR_STATUS_BASE (PCIE_CORE_BASE + 0x78)
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#define PCIE_CORE_PWR_OFFSET 0x100
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#define SR_A0_DEVICE_ID 0xd713
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#define SR_B0_DEVICE_ID 0xd714
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/* TODO: Modify device ID once available */
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#define NS3Z_DEVICE_ID 0xd715
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/* FIXME: change link speed to GEN3 when it's ready */
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#define GEN1_LINK_SPEED 1
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#define GEN2_LINK_SPEED 2
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#define GEN3_LINK_SPEED 3
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typedef struct {
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uint32_t type;
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uint32_t device_id;
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uint32_t pipemux_idx;
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uint32_t num_cores;
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int (*pipemux_init)(void);
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int (*phy_init)(void);
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int (*core_needs_enable)(unsigned int core_idx);
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unsigned int (*get_link_width)(unsigned int core_idx);
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unsigned int (*get_link_speed)(void);
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} paxb_cfg;
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enum paxb_type {
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PAXB_SR,
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PAXB_NS3Z,
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};
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extern const paxb_cfg *paxb;
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#ifdef USE_PAXB
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void paxb_init(void);
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void paxb_rc_cfg_write(unsigned int core_idx, unsigned int where,
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uint32_t val);
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unsigned int paxb_rc_cfg_read(unsigned int core_idx, unsigned int where);
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int pcie_core_needs_enable(unsigned int core_idx);
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const paxb_cfg *paxb_get_sr_config(void);
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#else
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static inline void paxb_init(void)
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{
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}
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#endif
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#endif /* PAXB_H */
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