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618 lines
16 KiB
618 lines
16 KiB
/*
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* Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <common/debug.h>
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#include <cortex_a57.h>
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#include <cpu_macros.S>
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* Clobbers: r0-r1
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* ---------------------------------------------
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*/
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func cortex_a57_disable_smp
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ldcopr16 r0, r1, CORTEX_A57_ECTLR
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bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT
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stcopr16 r0, r1, CORTEX_A57_ECTLR
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bx lr
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endfunc cortex_a57_disable_smp
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/* ---------------------------------------------
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* Disable all types of L2 prefetches.
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* Clobbers: r0-r2
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* ---------------------------------------------
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*/
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func cortex_a57_disable_l2_prefetch
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ldcopr16 r0, r1, CORTEX_A57_ECTLR
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orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT
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bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \
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CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK)
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stcopr16 r0, r1, CORTEX_A57_ECTLR
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isb
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dsb ish
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bx lr
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endfunc cortex_a57_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable debug interfaces
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* ---------------------------------------------
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*/
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func cortex_a57_disable_ext_debug
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mov r0, #1
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stcopr r0, DBGOSDLR
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isb
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#if ERRATA_A57_817169
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/*
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* Invalidate any TLB address
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*/
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mov r0, #0
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stcopr r0, TLBIMVA
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#endif
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dsb sy
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bx lr
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endfunc cortex_a57_disable_ext_debug
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/* --------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #806969.
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* This applies only to revision r0p0 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* --------------------------------------------------
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*/
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func errata_a57_806969_wa
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/*
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* Compare r0 against revision r0p0
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*/
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mov r2, lr
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bl check_errata_806969
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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1:
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bx lr
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endfunc errata_a57_806969_wa
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func check_errata_806969
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mov r1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_806969
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #813419.
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* This applies only to revision r0p0 of Cortex A57.
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* ---------------------------------------------------
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*/
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func check_errata_813419
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/*
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* Even though this is only needed for revision r0p0, it
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* is always applied due to limitations of the current
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* errata framework.
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*/
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mov r0, #ERRATA_APPLIES
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bx lr
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endfunc check_errata_813419
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #813420.
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* This applies only to revision r0p0 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a57_813420_wa
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/*
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* Compare r0 against revision r0p0
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*/
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mov r2, lr
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bl check_errata_813420
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DCC_AS_DCCI
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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1:
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bx lr
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endfunc errata_a57_813420_wa
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func check_errata_813420
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mov r1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_813420
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #814670.
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* This applies only to revision r0p0 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a57_814670_wa
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/*
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* Compare r0 against revision r0p0
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*/
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mov r2, lr
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bl check_errata_814670
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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isb
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1:
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bx r2
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endfunc errata_a57_814670_wa
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func check_errata_814670
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mov r1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_814670
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/* ----------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #817169.
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* This applies only to revision <= r0p1 of Cortex A57.
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* ----------------------------------------------------
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*/
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func check_errata_817169
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/*
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* Even though this is only needed for revision <= r0p1, it
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* is always applied because of the low cost of the workaround.
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*/
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mov r0, #ERRATA_APPLIES
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bx lr
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endfunc check_errata_817169
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/* --------------------------------------------------------------------
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* Disable the over-read from the LDNP instruction.
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*
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* This applies to all revisions <= r1p2. The performance degradation
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* observed with LDNP/STNP has been fixed on r1p3 and onwards.
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*
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------------------------
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*/
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func a57_disable_ldnp_overread
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/*
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* Compare r0 against revision r1p2
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*/
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mov r2, lr
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bl check_errata_disable_ldnp_overread
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_OVERREAD
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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1:
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bx lr
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endfunc a57_disable_ldnp_overread
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func check_errata_disable_ldnp_overread
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mov r1, #0x12
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b cpu_rev_var_ls
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endfunc check_errata_disable_ldnp_overread
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #826974.
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* This applies only to revision <= r1p1 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a57_826974_wa
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/*
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* Compare r0 against revision r1p1
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*/
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mov r2, lr
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bl check_errata_826974
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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1:
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bx lr
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endfunc errata_a57_826974_wa
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func check_errata_826974
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mov r1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_826974
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #826977.
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* This applies only to revision <= r1p1 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a57_826977_wa
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/*
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* Compare r0 against revision r1p1
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*/
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mov r2, lr
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bl check_errata_826977
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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orr64_imm r0, r1, CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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1:
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bx lr
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endfunc errata_a57_826977_wa
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func check_errata_826977
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mov r1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_826977
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #828024.
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* This applies only to revision <= r1p1 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a57_828024_wa
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/*
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* Compare r0 against revision r1p1
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*/
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mov r2, lr
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bl check_errata_828024
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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/*
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* Setting the relevant bits in CORTEX_A57_CPUACTLR has to be done in 2
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* instructions here because the resulting bitmask doesn't fit in a
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* 16-bit value so it cannot be encoded in a single instruction.
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*/
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orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
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orr64_imm r0, r1, (CORTEX_A57_CPUACTLR_DIS_L1_STREAMING | CORTEX_A57_CPUACTLR_DIS_STREAMING)
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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1:
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bx lr
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endfunc errata_a57_828024_wa
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func check_errata_828024
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mov r1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_828024
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #829520.
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* This applies only to revision <= r1p2 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a57_829520_wa
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/*
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* Compare r0 against revision r1p2
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*/
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mov r2, lr
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bl check_errata_829520
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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1:
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bx lr
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endfunc errata_a57_829520_wa
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func check_errata_829520
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mov r1, #0x12
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b cpu_rev_var_ls
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endfunc check_errata_829520
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #833471.
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* This applies only to revision <= r1p2 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a57_833471_wa
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/*
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* Compare r0 against revision r1p2
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*/
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mov r2, lr
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bl check_errata_833471
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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orr64_imm r1, r1, CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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1:
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bx lr
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endfunc errata_a57_833471_wa
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func check_errata_833471
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mov r1, #0x12
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b cpu_rev_var_ls
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endfunc check_errata_833471
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #859972.
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* This applies only to revision <= r1p3 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a57_859972_wa
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mov r2, lr
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bl check_errata_859972
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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orr64_imm r1, r1, CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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1:
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bx lr
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endfunc errata_a57_859972_wa
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func check_errata_859972
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mov r1, #0x13
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b cpu_rev_var_ls
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endfunc check_errata_859972
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func check_errata_cve_2017_5715
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mov r0, #ERRATA_MISSING
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bx lr
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endfunc check_errata_cve_2017_5715
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func check_errata_cve_2018_3639
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#if WORKAROUND_CVE_2018_3639
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mov r0, #ERRATA_APPLIES
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#else
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mov r0, #ERRATA_MISSING
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#endif
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bx lr
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endfunc check_errata_cve_2018_3639
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func check_errata_cve_2022_23960
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mov r0, #ERRATA_MISSING
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bx lr
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endfunc check_errata_cve_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A57.
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* Shall clobber: r0-r6
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* -------------------------------------------------
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*/
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func cortex_a57_reset_func
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mov r5, lr
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bl cpu_get_rev_var
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mov r4, r0
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#if ERRATA_A57_806969
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mov r0, r4
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bl errata_a57_806969_wa
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#endif
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#if ERRATA_A57_813420
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mov r0, r4
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bl errata_a57_813420_wa
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#endif
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#if ERRATA_A57_814670
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mov r0, r4
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bl errata_a57_814670_wa
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#endif
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#if A57_DISABLE_NON_TEMPORAL_HINT
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mov r0, r4
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bl a57_disable_ldnp_overread
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#endif
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#if ERRATA_A57_826974
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mov r0, r4
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bl errata_a57_826974_wa
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#endif
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#if ERRATA_A57_826977
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mov r0, r4
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bl errata_a57_826977_wa
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#endif
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#if ERRATA_A57_828024
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mov r0, r4
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bl errata_a57_828024_wa
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#endif
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#if ERRATA_A57_829520
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mov r0, r4
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bl errata_a57_829520_wa
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#endif
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#if ERRATA_A57_833471
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mov r0, r4
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bl errata_a57_833471_wa
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#endif
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#if ERRATA_A57_859972
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mov r0, r4
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bl errata_a57_859972_wa
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#endif
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#if WORKAROUND_CVE_2018_3639
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ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
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orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE
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stcopr16 r0, r1, CORTEX_A57_CPUACTLR
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isb
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dsb sy
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#endif
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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ldcopr16 r0, r1, CORTEX_A57_ECTLR
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orr64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT
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stcopr16 r0, r1, CORTEX_A57_ECTLR
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isb
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bx r5
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endfunc cortex_a57_reset_func
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Cortex-A57.
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* ----------------------------------------------------
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*/
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func cortex_a57_core_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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/* ---------------------------------------------
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* Disable the L2 prefetches.
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* ---------------------------------------------
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*/
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bl cortex_a57_disable_l2_prefetch
|
|
|
|
/* ---------------------------------------------
|
|
* Flush L1 caches.
|
|
* ---------------------------------------------
|
|
*/
|
|
mov r0, #DC_OP_CISW
|
|
bl dcsw_op_level1
|
|
|
|
/* ---------------------------------------------
|
|
* Come out of intra cluster coherency
|
|
* ---------------------------------------------
|
|
*/
|
|
bl cortex_a57_disable_smp
|
|
|
|
/* ---------------------------------------------
|
|
* Force the debug interfaces to be quiescent
|
|
* ---------------------------------------------
|
|
*/
|
|
pop {r12, lr}
|
|
b cortex_a57_disable_ext_debug
|
|
endfunc cortex_a57_core_pwr_dwn
|
|
|
|
/* -------------------------------------------------------
|
|
* The CPU Ops cluster power down function for Cortex-A57.
|
|
* Clobbers: r0-r3
|
|
* -------------------------------------------------------
|
|
*/
|
|
func cortex_a57_cluster_pwr_dwn
|
|
push {r12, lr}
|
|
|
|
/* Assert if cache is enabled */
|
|
#if ENABLE_ASSERTIONS
|
|
ldcopr r0, SCTLR
|
|
tst r0, #SCTLR_C_BIT
|
|
ASM_ASSERT(eq)
|
|
#endif
|
|
|
|
/* ---------------------------------------------
|
|
* Disable the L2 prefetches.
|
|
* ---------------------------------------------
|
|
*/
|
|
bl cortex_a57_disable_l2_prefetch
|
|
|
|
/* ---------------------------------------------
|
|
* Flush L1 caches.
|
|
* ---------------------------------------------
|
|
*/
|
|
mov r0, #DC_OP_CISW
|
|
bl dcsw_op_level1
|
|
|
|
/* ---------------------------------------------
|
|
* Disable the optional ACP.
|
|
* ---------------------------------------------
|
|
*/
|
|
bl plat_disable_acp
|
|
|
|
/* ---------------------------------------------
|
|
* Flush L2 caches.
|
|
* ---------------------------------------------
|
|
*/
|
|
mov r0, #DC_OP_CISW
|
|
bl dcsw_op_level2
|
|
|
|
/* ---------------------------------------------
|
|
* Come out of intra cluster coherency
|
|
* ---------------------------------------------
|
|
*/
|
|
bl cortex_a57_disable_smp
|
|
|
|
/* ---------------------------------------------
|
|
* Force the debug interfaces to be quiescent
|
|
* ---------------------------------------------
|
|
*/
|
|
pop {r12, lr}
|
|
b cortex_a57_disable_ext_debug
|
|
endfunc cortex_a57_cluster_pwr_dwn
|
|
|
|
#if REPORT_ERRATA
|
|
/*
|
|
* Errata printing function for Cortex A57. Must follow AAPCS.
|
|
*/
|
|
func cortex_a57_errata_report
|
|
push {r12, lr}
|
|
|
|
bl cpu_get_rev_var
|
|
mov r4, r0
|
|
|
|
/*
|
|
* Report all errata. The revision-variant information is passed to
|
|
* checking functions of each errata.
|
|
*/
|
|
report_errata ERRATA_A57_806969, cortex_a57, 806969
|
|
report_errata ERRATA_A57_813419, cortex_a57, 813419
|
|
report_errata ERRATA_A57_813420, cortex_a57, 813420
|
|
report_errata ERRATA_A57_814670, cortex_a57, 814670
|
|
report_errata ERRATA_A57_817169, cortex_a57, 817169
|
|
report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
|
|
disable_ldnp_overread
|
|
report_errata ERRATA_A57_826974, cortex_a57, 826974
|
|
report_errata ERRATA_A57_826977, cortex_a57, 826977
|
|
report_errata ERRATA_A57_828024, cortex_a57, 828024
|
|
report_errata ERRATA_A57_829520, cortex_a57, 829520
|
|
report_errata ERRATA_A57_833471, cortex_a57, 833471
|
|
report_errata ERRATA_A57_859972, cortex_a57, 859972
|
|
report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715
|
|
report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639
|
|
report_errata WORKAROUND_CVE_2022_23960, cortex_a57, cve_2022_23960
|
|
|
|
pop {r12, lr}
|
|
bx lr
|
|
endfunc cortex_a57_errata_report
|
|
#endif
|
|
|
|
declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \
|
|
cortex_a57_reset_func, \
|
|
cortex_a57_core_pwr_dwn, \
|
|
cortex_a57_cluster_pwr_dwn
|
|
|