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81 lines
1.9 KiB
81 lines
1.9 KiB
/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <cortex_a65ae.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if !HW_ASSISTED_COHERENCY
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#error "Cortex-A65AE must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS
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#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A65.
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* Shall clobber: x0-x19
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* -------------------------------------------------
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*/
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func cortex_a65ae_reset_func
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mov x19, x30
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#if ERRATA_DSU_936184
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bl errata_dsu_936184_wa
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#endif
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ret x19
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endfunc cortex_a65ae_reset_func
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func cortex_a65ae_cpu_pwr_dwn
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mrs x0, CORTEX_A65AE_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_A65AE_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a65ae_cpu_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex-A65AE. Must follow AAPCS.
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*/
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func cortex_a65ae_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_DSU_936184, cortex_a65ae, dsu_936184
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a65ae_errata_report
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#endif
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.section .rodata.cortex_a65ae_regs, "aS"
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cortex_a65ae_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a65ae_cpu_reg_dump
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adr x6, cortex_a65ae_regs
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mrs x8, CORTEX_A65AE_ECTLR_EL1
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ret
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endfunc cortex_a65ae_cpu_reg_dump
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declare_cpu_ops cortex_a65ae, CORTEX_A65AE_MIDR, \
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cortex_a65ae_reset_func, \
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cortex_a65ae_cpu_pwr_dwn
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