You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
138 lines
3.5 KiB
138 lines
3.5 KiB
/*
|
|
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#include <platform_def.h>
|
|
#include <xlat_tables_defs.h>
|
|
|
|
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
|
|
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
|
|
ENTRY(tsp_entrypoint)
|
|
|
|
|
|
MEMORY {
|
|
RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
|
|
}
|
|
|
|
|
|
SECTIONS
|
|
{
|
|
. = BL32_BASE;
|
|
ASSERT(. == ALIGN(PAGE_SIZE),
|
|
"BL32_BASE address is not aligned on a page boundary.")
|
|
|
|
#if SEPARATE_CODE_AND_RODATA
|
|
.text . : {
|
|
__TEXT_START__ = .;
|
|
*tsp_entrypoint.o(.text*)
|
|
*(.text*)
|
|
*(.vectors)
|
|
. = NEXT(PAGE_SIZE);
|
|
__TEXT_END__ = .;
|
|
} >RAM
|
|
|
|
.rodata . : {
|
|
__RODATA_START__ = .;
|
|
*(.rodata*)
|
|
. = NEXT(PAGE_SIZE);
|
|
__RODATA_END__ = .;
|
|
} >RAM
|
|
#else
|
|
ro . : {
|
|
__RO_START__ = .;
|
|
*tsp_entrypoint.o(.text*)
|
|
*(.text*)
|
|
*(.rodata*)
|
|
*(.vectors)
|
|
__RO_END_UNALIGNED__ = .;
|
|
/*
|
|
* Memory page(s) mapped to this section will be marked as
|
|
* read-only, executable. No RW data from the next section must
|
|
* creep in. Ensure the rest of the current memory page is unused.
|
|
*/
|
|
. = NEXT(PAGE_SIZE);
|
|
__RO_END__ = .;
|
|
} >RAM
|
|
#endif
|
|
|
|
/*
|
|
* Define a linker symbol to mark start of the RW memory area for this
|
|
* image.
|
|
*/
|
|
__RW_START__ = . ;
|
|
|
|
.data . : {
|
|
__DATA_START__ = .;
|
|
*(.data*)
|
|
__DATA_END__ = .;
|
|
} >RAM
|
|
|
|
#ifdef TSP_PROGBITS_LIMIT
|
|
ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
|
|
#endif
|
|
|
|
stacks (NOLOAD) : {
|
|
__STACKS_START__ = .;
|
|
*(tzfw_normal_stacks)
|
|
__STACKS_END__ = .;
|
|
} >RAM
|
|
|
|
/*
|
|
* The .bss section gets initialised to 0 at runtime.
|
|
* Its base address should be 16-byte aligned for better performance of the
|
|
* zero-initialization code.
|
|
*/
|
|
.bss : ALIGN(16) {
|
|
__BSS_START__ = .;
|
|
*(SORT_BY_ALIGNMENT(.bss*))
|
|
*(COMMON)
|
|
__BSS_END__ = .;
|
|
} >RAM
|
|
|
|
/*
|
|
* The xlat_table section is for full, aligned page tables (4K).
|
|
* Removing them from .bss avoids forcing 4K alignment on
|
|
* the .bss section and eliminates the unecessary zero init
|
|
*/
|
|
xlat_table (NOLOAD) : {
|
|
*(xlat_table)
|
|
} >RAM
|
|
|
|
#if USE_COHERENT_MEM
|
|
/*
|
|
* The base address of the coherent memory section must be page-aligned (4K)
|
|
* to guarantee that the coherent data are stored on their own pages and
|
|
* are not mixed with normal data. This is required to set up the correct
|
|
* memory attributes for the coherent data page tables.
|
|
*/
|
|
coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
|
|
__COHERENT_RAM_START__ = .;
|
|
*(tzfw_coherent_mem)
|
|
__COHERENT_RAM_END_UNALIGNED__ = .;
|
|
/*
|
|
* Memory page(s) mapped to this section will be marked
|
|
* as device memory. No other unexpected data must creep in.
|
|
* Ensure the rest of the current memory page is unused.
|
|
*/
|
|
. = NEXT(PAGE_SIZE);
|
|
__COHERENT_RAM_END__ = .;
|
|
} >RAM
|
|
#endif
|
|
|
|
/*
|
|
* Define a linker symbol to mark the end of the RW memory area for this
|
|
* image.
|
|
*/
|
|
__RW_END__ = .;
|
|
__BL32_END__ = .;
|
|
|
|
__BSS_SIZE__ = SIZEOF(.bss);
|
|
#if USE_COHERENT_MEM
|
|
__COHERENT_RAM_UNALIGNED_SIZE__ =
|
|
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
|
|
#endif
|
|
|
|
ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
|
|
}
|
|
|