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299 lines
5.5 KiB
299 lines
5.5 KiB
/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
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/*
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* Copyright (C) 2020-2024 STMicroelectronics - All Rights Reserved
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* Copyright (C) 2020 Ahmad Fatoum, Pengutronix
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*/
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#include "stm32mp15-pinctrl.dtsi"
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_a>;
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clock-frequency = <400000>;
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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status = "okay";
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pmic: stpmic@33 {
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compatible = "st,stpmic1";
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reg = <0x33>;
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interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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regulators {
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compatible = "st,stpmic1-regulators";
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ldo1-supply = <&v3v3>;
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ldo6-supply = <&v3v3>;
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pwr_sw1-supply = <&bst_out>;
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vddcore: buck1 {
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regulator-name = "vddcore";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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vdd_ddr: buck2 {
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regulator-name = "vdd_ddr";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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vdd: buck3 {
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regulator-name = "vdd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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st,mask-reset;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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v3v3: buck4 {
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regulator-name = "v3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-over-current-protection;
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regulator-initial-mode = <0>;
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};
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v1v8_audio: ldo1 {
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regulator-name = "v1v8_audio";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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v3v3_hdmi: ldo2 {
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regulator-name = "v3v3_hdmi";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vtt_ddr: ldo3 {
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regulator-name = "vtt_ddr";
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regulator-always-on;
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regulator-over-current-protection;
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st,regulator-sink-source;
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};
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vdd_usb: ldo4 {
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regulator-name = "vdd_usb";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vdda: ldo5 {
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regulator-name = "vdda";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <2900000>;
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regulator-boot-on;
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};
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v1v2_hdmi: ldo6 {
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regulator-name = "v1v2_hdmi";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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};
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vref_ddr: vref_ddr {
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regulator-name = "vref_ddr";
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regulator-always-on;
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};
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bst_out: boost {
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regulator-name = "bst_out";
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};
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vbus_otg: pwr_sw1 {
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regulator-name = "vbus_otg";
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regulator-active-discharge;
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};
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vbus_sw: pwr_sw2 {
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regulator-name = "vbus_sw";
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regulator-active-discharge;
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};
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};
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pmic_watchdog: watchdog {
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compatible = "st,stpmic1-wdt";
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status = "disabled";
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};
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};
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};
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&rng1 {
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status = "okay";
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};
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/* ATF Specific */
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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/ {
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio25 = &gpioz;
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i2c3 = &i2c4;
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};
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};
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&bsec {
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board_id: board-id@ec {
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reg = <0xec 0x4>;
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st,non-secure-otp;
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};
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};
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&clk_hse {
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st,digbypass;
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};
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&cpu0 {
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cpu-supply = <&vddcore>;
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};
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&cpu1 {
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cpu-supply = <&vddcore>;
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};
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&hash1 {
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status = "okay";
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};
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/* CLOCK init */
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&rcc {
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_PLL4P
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CLK_SDMMC12_PLL4P
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
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CLK_SPI45_HSI
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CLK_SPI6_HSI
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CLK_I2C46_HSI
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CLK_SDMMC3_PLL4P
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CLK_USBO_USBPHY
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CLK_ADC_CKPER
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CLK_CEC_LSE
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CLK_I2C12_HSI
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CLK_I2C35_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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CLK_UART35_HSI
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4R
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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CLK_SAI4_PLL3Q
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CLK_RNG1_CSI
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CLK_RNG2_LSI
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CLK_LPTIM1_PCLK1
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CLK_LPTIM23_PCLK3
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CLK_LPTIM45_LSE
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>;
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st,clkdiv = <
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DIV(DIV_MPU, 1)
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DIV(DIV_AXI, 0)
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DIV(DIV_MCU, 0)
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DIV(DIV_APB1, 1)
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DIV(DIV_APB2, 1)
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DIV(DIV_APB3, 1)
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DIV(DIV_APB4, 1)
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DIV(DIV_APB5, 2)
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DIV(DIV_RTC, 23)
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DIV(DIV_MCO1, 0)
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DIV(DIV_MCO2, 0)
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>;
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st,pll_vco {
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pll2_vco_1066Mhz: pll2-vco-1066Mhz {
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src = <CLK_PLL12_HSE>;
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divmn = <2 65>;
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frac = <0x1400>;
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};
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pll3_vco_417Mhz: pll3-vco-417Mhz {
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src = <CLK_PLL3_HSE>;
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divmn = <1 33>;
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frac = <0x1a04>;
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};
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pll4_vco_594Mhz: pll4-vco-594Mhz {
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src = <CLK_PLL4_HSE>;
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divmn = <3 98>;
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};
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};
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
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pll2: st,pll@1 {
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compatible = "st,stm32mp1-pll";
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reg = <1>;
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st,pll = <&pll2_cfg1>;
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pll2_cfg1: pll2_cfg1 {
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st,pll_vco = <&pll2_vco_1066Mhz>;
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st,pll_div_pqr = <1 0 0>;
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};
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};
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/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
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pll3: st,pll@2 {
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compatible = "st,stm32mp1-pll";
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reg = <2>;
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st,pll = <&pll3_cfg1>;
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pll3_cfg1: pll3_cfg1 {
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st,pll_vco = <&pll3_vco_417Mhz>;
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st,pll_div_pqr = <1 16 36>;
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};
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};
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/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
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pll4: st,pll@3 {
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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st,pll = <&pll4_cfg1>;
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pll4_cfg1: pll4_cfg1 {
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st,pll_vco = <&pll4_vco_594Mhz>;
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st,pll_div_pqr = <5 7 7>;
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};
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};
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};
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