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280 lines
8.4 KiB
280 lines
8.4 KiB
/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __GIC_V2_H__
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#define __GIC_V2_H__
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/* The macros required here are additional to those in gic_common.h. */
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#include <gic_common.h>
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/******************************************************************************
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* THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h
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* and for GICv3 systems, use the driver in gicv3.h.
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*****************************************************************************/
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#if ERROR_DEPRECATED
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#error " The legacy ARM GIC driver is deprecated."
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#endif
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#define GIC400_NUM_SPIS U(480)
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#define MAX_PPIS U(14)
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#define MAX_SGIS U(16)
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#define GRP0 U(0)
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#define GRP1 U(1)
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#define GIC_TARGET_CPU_MASK U(0xff)
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#define ENABLE_GRP0 (U(1) << 0)
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#define ENABLE_GRP1 (U(1) << 1)
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/* Distributor interface definitions */
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#define GICD_ITARGETSR U(0x800)
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#define GICD_SGIR U(0xF00)
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#define GICD_CPENDSGIR U(0xF10)
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#define GICD_SPENDSGIR U(0xF20)
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#define CPENDSGIR_SHIFT U(2)
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#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
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/* GICD_TYPER bit definitions */
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#define IT_LINES_NO_MASK U(0x1f)
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/* Physical CPU Interface registers */
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#define GICC_CTLR U(0x0)
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#define GICC_PMR U(0x4)
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#define GICC_BPR U(0x8)
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#define GICC_IAR U(0xC)
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#define GICC_EOIR U(0x10)
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#define GICC_RPR U(0x14)
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#define GICC_HPPIR U(0x18)
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#define GICC_AHPPIR U(0x28)
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#define GICC_IIDR U(0xFC)
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#define GICC_DIR U(0x1000)
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#define GICC_PRIODROP GICC_EOIR
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/* Common CPU Interface definitions */
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#define INT_ID_MASK U(0x3ff)
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/* GICC_CTLR bit definitions */
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#define EOI_MODE_NS (U(1) << 10)
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#define EOI_MODE_S (U(1) << 9)
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#define IRQ_BYP_DIS_GRP1 (U(1) << 8)
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#define FIQ_BYP_DIS_GRP1 (U(1) << 7)
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#define IRQ_BYP_DIS_GRP0 (U(1) << 6)
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#define FIQ_BYP_DIS_GRP0 (U(1) << 5)
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#define CBPR (U(1) << 4)
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#define FIQ_EN (U(1) << 3)
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#define ACK_CTL (U(1) << 2)
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/* GICC_IIDR bit masks and shifts */
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#define GICC_IIDR_PID_SHIFT U(20)
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#define GICC_IIDR_ARCH_SHIFT U(16)
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#define GICC_IIDR_REV_SHIFT U(12)
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#define GICC_IIDR_IMP_SHIFT U(0)
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#define GICC_IIDR_PID_MASK U(0xfff)
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#define GICC_IIDR_ARCH_MASK U(0xf)
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#define GICC_IIDR_REV_MASK U(0xf)
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#define GICC_IIDR_IMP_MASK U(0xfff)
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/* HYP view virtual CPU Interface registers */
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#define GICH_CTL U(0x0)
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#define GICH_VTR U(0x4)
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#define GICH_ELRSR0 U(0x30)
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#define GICH_ELRSR1 U(0x34)
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#define GICH_APR0 U(0xF0)
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#define GICH_LR_BASE U(0x100)
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/* Virtual CPU Interface registers */
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#define GICV_CTL U(0x0)
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#define GICV_PRIMASK U(0x4)
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#define GICV_BP U(0x8)
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#define GICV_INTACK U(0xC)
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#define GICV_EOI U(0x10)
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#define GICV_RUNNINGPRI U(0x14)
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#define GICV_HIGHESTPEND U(0x18)
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#define GICV_DEACTIVATE U(0x1000)
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#ifndef __ASSEMBLY__
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#include <mmio.h>
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#include <stdint.h>
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/*******************************************************************************
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* GIC Distributor function prototypes
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******************************************************************************/
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unsigned int gicd_read_igroupr(uintptr_t, unsigned int);
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unsigned int gicd_read_isenabler(uintptr_t, unsigned int);
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unsigned int gicd_read_icenabler(uintptr_t, unsigned int);
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unsigned int gicd_read_ispendr(uintptr_t, unsigned int);
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unsigned int gicd_read_icpendr(uintptr_t, unsigned int);
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unsigned int gicd_read_isactiver(uintptr_t, unsigned int);
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unsigned int gicd_read_icactiver(uintptr_t, unsigned int);
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unsigned int gicd_read_ipriorityr(uintptr_t, unsigned int);
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unsigned int gicd_read_itargetsr(uintptr_t, unsigned int);
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unsigned int gicd_read_icfgr(uintptr_t, unsigned int);
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unsigned int gicd_read_cpendsgir(uintptr_t, unsigned int);
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unsigned int gicd_read_spendsgir(uintptr_t, unsigned int);
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void gicd_write_igroupr(uintptr_t, unsigned int, unsigned int);
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void gicd_write_isenabler(uintptr_t, unsigned int, unsigned int);
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void gicd_write_icenabler(uintptr_t, unsigned int, unsigned int);
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void gicd_write_ispendr(uintptr_t, unsigned int, unsigned int);
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void gicd_write_icpendr(uintptr_t, unsigned int, unsigned int);
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void gicd_write_isactiver(uintptr_t, unsigned int, unsigned int);
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void gicd_write_icactiver(uintptr_t, unsigned int, unsigned int);
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void gicd_write_ipriorityr(uintptr_t, unsigned int, unsigned int);
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void gicd_write_itargetsr(uintptr_t, unsigned int, unsigned int);
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void gicd_write_icfgr(uintptr_t, unsigned int, unsigned int);
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void gicd_write_cpendsgir(uintptr_t, unsigned int, unsigned int);
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void gicd_write_spendsgir(uintptr_t, unsigned int, unsigned int);
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unsigned int gicd_get_igroupr(uintptr_t, unsigned int);
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void gicd_set_igroupr(uintptr_t, unsigned int);
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void gicd_clr_igroupr(uintptr_t, unsigned int);
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void gicd_set_isenabler(uintptr_t, unsigned int);
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void gicd_set_icenabler(uintptr_t, unsigned int);
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void gicd_set_ispendr(uintptr_t, unsigned int);
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void gicd_set_icpendr(uintptr_t, unsigned int);
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void gicd_set_isactiver(uintptr_t, unsigned int);
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void gicd_set_icactiver(uintptr_t, unsigned int);
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void gicd_set_ipriorityr(uintptr_t, unsigned int, unsigned int);
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void gicd_set_itargetsr(uintptr_t, unsigned int, unsigned int);
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/*******************************************************************************
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* GIC Distributor interface accessors for reading entire registers
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******************************************************************************/
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static inline unsigned int gicd_read_ctlr(uintptr_t base)
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{
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return mmio_read_32(base + GICD_CTLR);
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}
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static inline unsigned int gicd_read_typer(uintptr_t base)
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{
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return mmio_read_32(base + GICD_TYPER);
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}
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static inline unsigned int gicd_read_sgir(uintptr_t base)
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{
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return mmio_read_32(base + GICD_SGIR);
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}
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/*******************************************************************************
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* GIC Distributor interface accessors for writing entire registers
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******************************************************************************/
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static inline void gicd_write_ctlr(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICD_CTLR, val);
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}
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static inline void gicd_write_sgir(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICD_SGIR, val);
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}
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/*******************************************************************************
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* GIC CPU interface accessors for reading entire registers
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******************************************************************************/
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static inline unsigned int gicc_read_ctlr(uintptr_t base)
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{
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return mmio_read_32(base + GICC_CTLR);
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}
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static inline unsigned int gicc_read_pmr(uintptr_t base)
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{
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return mmio_read_32(base + GICC_PMR);
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}
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static inline unsigned int gicc_read_BPR(uintptr_t base)
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{
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return mmio_read_32(base + GICC_BPR);
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}
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static inline unsigned int gicc_read_IAR(uintptr_t base)
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{
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return mmio_read_32(base + GICC_IAR);
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}
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static inline unsigned int gicc_read_EOIR(uintptr_t base)
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{
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return mmio_read_32(base + GICC_EOIR);
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}
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static inline unsigned int gicc_read_hppir(uintptr_t base)
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{
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return mmio_read_32(base + GICC_HPPIR);
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}
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static inline unsigned int gicc_read_ahppir(uintptr_t base)
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{
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return mmio_read_32(base + GICC_AHPPIR);
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}
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static inline unsigned int gicc_read_dir(uintptr_t base)
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{
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return mmio_read_32(base + GICC_DIR);
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}
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static inline unsigned int gicc_read_iidr(uintptr_t base)
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{
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return mmio_read_32(base + GICC_IIDR);
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}
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/*******************************************************************************
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* GIC CPU interface accessors for writing entire registers
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******************************************************************************/
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static inline void gicc_write_ctlr(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_CTLR, val);
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}
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static inline void gicc_write_pmr(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_PMR, val);
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}
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static inline void gicc_write_BPR(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_BPR, val);
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}
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static inline void gicc_write_IAR(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_IAR, val);
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}
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static inline void gicc_write_EOIR(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_EOIR, val);
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}
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static inline void gicc_write_hppir(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_HPPIR, val);
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}
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static inline void gicc_write_dir(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_DIR, val);
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}
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/*******************************************************************************
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* Prototype of function to map an interrupt type to the interrupt line used to
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* signal it.
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******************************************************************************/
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uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type);
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#endif /*__ASSEMBLY__*/
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#endif /* __GIC_V2_H__ */
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