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151 lines
3.2 KiB
151 lines
3.2 KiB
/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include "morello.dtsi"
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/ {
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chosen {
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stdout-path = "serial0:115200n8";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure-firmware@ff000000 {
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reg = <0 0xff000000 0 0x01000000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0@0 {
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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cpu1@100 {
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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cpu2@10000 {
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compatible = "arm,armv8";
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reg = <0x0 0x10000>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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cpu3@10100 {
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compatible = "arm,armv8";
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reg = <0x0 0x10100>;
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device_type = "cpu";
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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};
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};
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/* The first bank of memory, memory map is actually provided by UEFI. */
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memory@80000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "memory";
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/* [0x80000000-0xffffffff] */
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reg = <0x00000000 0x80000000 0x0 0x80000000>;
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};
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memory@8080000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "memory";
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/* [0x8080000000-0x83ffffffff] */
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reg = <0x00000080 0x80000000 0x1 0x80000000>;
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};
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virtio_block@1c170000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c170000 0x0 0x200>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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};
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virtio_net@1c180000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c180000 0x0 0x200>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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};
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virtio_rng@1c190000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c190000 0x0 0x200>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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};
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virtio_p9@1c1a0000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c1a0000 0x0 0x200>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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};
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ethernet@1d100000 {
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compatible = "smsc,lan91c111";
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reg = <0x0 0x1d100000 0x0 0x10000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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};
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kmi@1c150000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x1c150000 0x0 0x1000>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@1c160000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x1c160000 0x0 0x1000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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firmware {
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scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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mboxes = <&mailbox 1 0 &mailbox 1 1>;
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shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_dvfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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};
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};
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bp_clock24mhz: clock24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "bp:clock24mhz";
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};
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};
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&gic {
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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<0x0 0x300c0000 0 0x80000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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