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Joanna Farley 7f95003bdb Merge "build(fvp): reduce the number of cpu libraries included by default" into integration 2 years ago
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allwinner refactor(cpufeat): rename ENABLE_SPE_FOR_LOWER_ELS to ENABLE_SPE_FOR_NS 2 years ago
amlogic Plat AXG: Fix PLAT_MAX_PWR_LVL value 4 years ago
arm build(fvp): reduce the number of cpu libraries included by default 2 years ago
brcm refactor(libc): clean up dependencies in libc 2 years ago
common Merge changes from topic "panic_cleanup" into integration 2 years ago
hisilicon refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 2 years ago
imx feat(imx8): add support for debug uart on lpuart1 2 years ago
intel/soc fix(intel): fix Agilex and N5X clock manager to main PLL C0 2 years ago
marvell build: always prefix section names with `.` 2 years ago
mediatek feat(mt8188): add apu power on/off control 2 years ago
nvidia/tegra Merge "fix(tegra): append major revision to the chip_id value" into integration 2 years ago
nxp refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 2 years ago
qemu feat(qemu): increase max cpus per cluster to 16 2 years ago
qti Merge changes from topic "psci-osi" into integration 2 years ago
renesas refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 2 years ago
rockchip style: remove useless trailing semicolon and line continuations 2 years ago
rpi fix(rpi3): initialize SD card host controller 2 years ago
socionext refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 2 years ago
st refactor(auth)!: unify REGISTER_CRYPTO_LIB 2 years ago
ti/k3 feat(ti): synchronize access to secure proxy threads 2 years ago
xilinx Merge "style(xilinx): fix AMD copyright format" into integration 2 years ago