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141 lines
3.7 KiB
141 lines
3.7 KiB
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* ARM PL061 GPIO Driver.
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* Reference to ARM DDI 0190B document.
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*
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*/
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#include <assert.h>
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#include <cassert.h>
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#include <debug.h>
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#include <errno.h>
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#include <gpio.h>
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#include <mmio.h>
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#include <pl061_gpio.h>
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#include <utils.h>
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#if !PLAT_PL061_MAX_GPIOS
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# define PLAT_PL061_MAX_GPIOS 32
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#endif /* PLAT_PL061_MAX_GPIOS */
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CASSERT(PLAT_PL061_MAX_GPIOS > 0, assert_plat_pl061_max_gpios);
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#define MAX_GPIO_DEVICES ((PLAT_PL061_MAX_GPIOS + \
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(GPIOS_PER_PL061 - 1)) / GPIOS_PER_PL061)
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#define PL061_GPIO_DIR 0x400
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#define GPIOS_PER_PL061 8
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static int pl061_get_direction(int gpio);
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static void pl061_set_direction(int gpio, int direction);
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static int pl061_get_value(int gpio);
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static void pl061_set_value(int gpio, int value);
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static uintptr_t pl061_reg_base[MAX_GPIO_DEVICES];
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static const gpio_ops_t pl061_gpio_ops = {
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.get_direction = pl061_get_direction,
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.set_direction = pl061_set_direction,
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.get_value = pl061_get_value,
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.set_value = pl061_set_value,
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};
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static int pl061_get_direction(int gpio)
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{
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uintptr_t base_addr;
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unsigned int data, offset;
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assert((gpio >= 0) && (gpio < PLAT_PL061_MAX_GPIOS));
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base_addr = pl061_reg_base[gpio / GPIOS_PER_PL061];
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offset = gpio % GPIOS_PER_PL061;
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data = mmio_read_8(base_addr + PL061_GPIO_DIR);
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if (data & BIT(offset))
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return GPIO_DIR_OUT;
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return GPIO_DIR_IN;
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}
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static void pl061_set_direction(int gpio, int direction)
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{
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uintptr_t base_addr;
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unsigned int data, offset;
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assert((gpio >= 0) && (gpio < PLAT_PL061_MAX_GPIOS));
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base_addr = pl061_reg_base[gpio / GPIOS_PER_PL061];
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offset = gpio % GPIOS_PER_PL061;
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if (direction == GPIO_DIR_OUT) {
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data = mmio_read_8(base_addr + PL061_GPIO_DIR) | BIT(offset);
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mmio_write_8(base_addr + PL061_GPIO_DIR, data);
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} else {
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data = mmio_read_8(base_addr + PL061_GPIO_DIR) & ~BIT(offset);
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mmio_write_8(base_addr + PL061_GPIO_DIR, data);
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}
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}
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/*
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* The offset of GPIODATA register is 0.
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* The values read from GPIODATA are determined for each bit, by the mask bit
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* derived from the address used to access the data register, PADDR[9:2].
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* Bits that are 1 in the address mask cause the corresponding bits in GPIODATA
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* to be read, and bits that are 0 in the address mask cause the corresponding
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* bits in GPIODATA to be read as 0, regardless of their value.
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*/
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static int pl061_get_value(int gpio)
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{
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uintptr_t base_addr;
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unsigned int offset;
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assert((gpio >= 0) && (gpio < PLAT_PL061_MAX_GPIOS));
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base_addr = pl061_reg_base[gpio / GPIOS_PER_PL061];
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offset = gpio % GPIOS_PER_PL061;
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if (mmio_read_8(base_addr + BIT(offset + 2)))
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return GPIO_LEVEL_HIGH;
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return GPIO_LEVEL_LOW;
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}
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/*
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* In order to write GPIODATA, the corresponding bits in the mask, resulting
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* from the address bus, PADDR[9:2], must be HIGH. Otherwise the bit values
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* remain unchanged by the write.
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*/
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static void pl061_set_value(int gpio, int value)
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{
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uintptr_t base_addr;
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int offset;
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assert((gpio >= 0) && (gpio < PLAT_PL061_MAX_GPIOS));
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base_addr = pl061_reg_base[gpio / GPIOS_PER_PL061];
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offset = gpio % GPIOS_PER_PL061;
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if (value == GPIO_LEVEL_HIGH)
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mmio_write_8(base_addr + BIT(offset + 2), BIT(offset));
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else
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mmio_write_8(base_addr + BIT(offset + 2), 0);
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}
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/*
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* Register the PL061 GPIO controller with a base address and the offset
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* of start pin in this GPIO controller.
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* This function is called after pl061_gpio_ops_init().
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*/
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void pl061_gpio_register(uintptr_t base_addr, int gpio_dev)
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{
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assert((gpio_dev >= 0) && (gpio_dev < MAX_GPIO_DEVICES));
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pl061_reg_base[gpio_dev] = base_addr;
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}
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/*
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* Initialize PL061 GPIO controller with the total GPIO numbers in SoC.
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*/
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void pl061_gpio_init(void)
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{
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gpio_init(&pl061_gpio_ops);
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}
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