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214 lines
6.1 KiB
214 lines
6.1 KiB
/*
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* Copyright (C) 2016 - 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* IOW unit device driver for Marvell CP110 and CP115 SoCs */
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#include <inttypes.h>
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#include <stdint.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/marvell/iob.h>
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#include <lib/mmio.h>
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#include <armada_common.h>
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#include <mvebu.h>
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#include <mvebu_def.h>
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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#define DEBUG_ADDR_MAP
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#endif
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#define MVEBU_IOB_OFFSET (0x190000)
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#define MVEBU_IOB_MAX_WINS 16
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/* common defines */
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#define WIN_ENABLE_BIT (0x1)
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/* Physical address of the base of the window = {AddrLow[19:0],20`h0} */
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#define ADDRESS_SHIFT (20 - 4)
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#define ADDRESS_MASK (0xFFFFFFF0)
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#define IOB_WIN_ALIGNMENT (0x100000)
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/* IOB registers */
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#define IOB_WIN_CR_OFFSET(win) (iob_base + 0x0 + (0x20 * win))
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#define IOB_TARGET_ID_OFFSET (8)
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#define IOB_TARGET_ID_MASK (0xF)
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#define IOB_WIN_SCR_OFFSET(win) (iob_base + 0x4 + (0x20 * win))
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#define IOB_WIN_ENA_CTRL_WRITE_SECURE (0x1)
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#define IOB_WIN_ENA_CTRL_READ_SECURE (0x2)
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#define IOB_WIN_ENA_WRITE_SECURE (0x4)
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#define IOB_WIN_ENA_READ_SECURE (0x8)
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#define IOB_WIN_ALR_OFFSET(win) (iob_base + 0x8 + (0x20 * win))
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#define IOB_WIN_AHR_OFFSET(win) (iob_base + 0xC + (0x20 * win))
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#define IOB_WIN_DIOB_CR_OFFSET(win) (iob_base + 0x10 + (0x20 * win))
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#define IOB_WIN_XOR0_DIOB_EN BIT(0)
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#define IOB_WIN_XOR1_DIOB_EN BIT(1)
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uintptr_t iob_base;
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static void iob_win_check(struct addr_map_win *win, uint32_t win_num)
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{
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/* check if address is aligned to the size */
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if (IS_NOT_ALIGN(win->base_addr, IOB_WIN_ALIGNMENT)) {
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win->base_addr = ALIGN_UP(win->base_addr, IOB_WIN_ALIGNMENT);
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ERROR("Window %d: base address unaligned to 0x%x\n",
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win_num, IOB_WIN_ALIGNMENT);
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printf("Align up the base address to 0x%" PRIx64 "\n",
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win->base_addr);
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}
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/* size parameter validity check */
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if (IS_NOT_ALIGN(win->win_size, IOB_WIN_ALIGNMENT)) {
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win->win_size = ALIGN_UP(win->win_size, IOB_WIN_ALIGNMENT);
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ERROR("Window %d: window size unaligned to 0x%x\n", win_num,
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IOB_WIN_ALIGNMENT);
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printf("Aligning size to 0x%" PRIx64 "\n", win->win_size);
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}
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}
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static void iob_enable_win(struct addr_map_win *win, uint32_t win_id)
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{
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uint32_t iob_win_reg;
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uint32_t alr, ahr;
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uint64_t end_addr;
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uint32_t reg_en;
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/* move XOR (DMA) to use WIN1 which is used for PCI-EP address space */
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reg_en = IOB_WIN_XOR0_DIOB_EN | IOB_WIN_XOR1_DIOB_EN;
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iob_win_reg = mmio_read_32(IOB_WIN_DIOB_CR_OFFSET(0));
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iob_win_reg &= ~reg_en;
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mmio_write_32(IOB_WIN_DIOB_CR_OFFSET(0), iob_win_reg);
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iob_win_reg = mmio_read_32(IOB_WIN_DIOB_CR_OFFSET(1));
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iob_win_reg |= reg_en;
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mmio_write_32(IOB_WIN_DIOB_CR_OFFSET(1), iob_win_reg);
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end_addr = (win->base_addr + win->win_size - 1);
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alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
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ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
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mmio_write_32(IOB_WIN_ALR_OFFSET(win_id), alr);
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mmio_write_32(IOB_WIN_AHR_OFFSET(win_id), ahr);
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iob_win_reg = WIN_ENABLE_BIT;
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iob_win_reg |= (win->target_id & IOB_TARGET_ID_MASK)
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<< IOB_TARGET_ID_OFFSET;
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mmio_write_32(IOB_WIN_CR_OFFSET(win_id), iob_win_reg);
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}
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#ifdef DEBUG_ADDR_MAP
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static void dump_iob(void)
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{
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uint32_t win_id, win_cr, alr, ahr;
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uint8_t target_id;
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uint64_t start, end;
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char *iob_target_name[IOB_MAX_TID] = {
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"CFG ", "MCI0 ", "PEX1 ", "PEX2 ",
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"PEX0 ", "NAND ", "RUNIT", "MCI1 " };
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/* Dump all IOB windows */
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printf("bank id target start end\n");
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printf("----------------------------------------------------\n");
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for (win_id = 0; win_id < MVEBU_IOB_MAX_WINS; win_id++) {
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win_cr = mmio_read_32(IOB_WIN_CR_OFFSET(win_id));
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if (win_cr & WIN_ENABLE_BIT) {
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target_id = (win_cr >> IOB_TARGET_ID_OFFSET) &
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IOB_TARGET_ID_MASK;
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alr = mmio_read_32(IOB_WIN_ALR_OFFSET(win_id));
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start = ((uint64_t)alr << ADDRESS_SHIFT);
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if (win_id != 0) {
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ahr = mmio_read_32(IOB_WIN_AHR_OFFSET(win_id));
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end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT);
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} else {
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/* Window #0 size is hardcoded to 16MB, as it's
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* reserved for CP configuration space.
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*/
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end = start + (16 << 20);
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}
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printf("iob %02d %s 0x%016" PRIx64 " 0x%016" PRIx64 "\n",
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win_id, iob_target_name[target_id],
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start, end);
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}
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}
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}
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#endif
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void iob_cfg_space_update(int ap_idx, int cp_idx, uintptr_t base,
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uintptr_t new_base)
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{
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debug_enter();
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iob_base = base + MVEBU_IOB_OFFSET;
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NOTICE("Change the base address of AP%d-CP%d to %lx\n",
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ap_idx, cp_idx, new_base);
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mmio_write_32(IOB_WIN_ALR_OFFSET(0), new_base >> ADDRESS_SHIFT);
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iob_base = new_base + MVEBU_IOB_OFFSET;
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/* Make sure the address was configured by the CPU before
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* any possible access to the CP.
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*/
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dsb();
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debug_exit();
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}
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int init_iob(uintptr_t base)
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{
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struct addr_map_win *win;
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uint32_t win_id, win_reg;
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uint32_t win_count;
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INFO("Initializing IOB Address decoding\n");
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/* Get the base address of the address decoding MBUS */
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iob_base = base + MVEBU_IOB_OFFSET;
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/* Get the array of the windows and fill the map data */
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marvell_get_iob_memory_map(&win, &win_count, base);
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if (win_count <= 0) {
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INFO("no windows configurations found\n");
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return 0;
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} else if (win_count > (MVEBU_IOB_MAX_WINS - 1)) {
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ERROR("IOB mem map array > than max available windows (%d)\n",
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MVEBU_IOB_MAX_WINS);
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win_count = MVEBU_IOB_MAX_WINS;
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}
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/* disable all IOB windows, start from win_id = 1
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* because can't disable internal register window
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*/
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for (win_id = 1; win_id < MVEBU_IOB_MAX_WINS; win_id++) {
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win_reg = mmio_read_32(IOB_WIN_CR_OFFSET(win_id));
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win_reg &= ~WIN_ENABLE_BIT;
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mmio_write_32(IOB_WIN_CR_OFFSET(win_id), win_reg);
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win_reg = ~IOB_WIN_ENA_CTRL_WRITE_SECURE;
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win_reg &= ~IOB_WIN_ENA_CTRL_READ_SECURE;
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win_reg &= ~IOB_WIN_ENA_WRITE_SECURE;
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win_reg &= ~IOB_WIN_ENA_READ_SECURE;
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mmio_write_32(IOB_WIN_SCR_OFFSET(win_id), win_reg);
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}
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for (win_id = 1; win_id < win_count + 1; win_id++, win++) {
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iob_win_check(win, win_id);
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iob_enable_win(win, win_id);
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}
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#ifdef DEBUG_ADDR_MAP
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dump_iob();
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#endif
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INFO("Done IOB Address decoding Initializing\n");
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return 0;
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}
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