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157 lines
5.1 KiB
157 lines
5.1 KiB
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CCI_H__
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#define __CCI_H__
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/* Slave interface offsets from PERIPHBASE */
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#define SLAVE_IFACE6_OFFSET 0x7000
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#define SLAVE_IFACE5_OFFSET 0x6000
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#define SLAVE_IFACE4_OFFSET 0x5000
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#define SLAVE_IFACE3_OFFSET 0x4000
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#define SLAVE_IFACE2_OFFSET 0x3000
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#define SLAVE_IFACE1_OFFSET 0x2000
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#define SLAVE_IFACE0_OFFSET 0x1000
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#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \
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(0x1000 * (index)))
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/* Slave interface event and count register offsets from PERIPHBASE */
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#define EVENT_SELECT7_OFFSET 0x80000
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#define EVENT_SELECT6_OFFSET 0x70000
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#define EVENT_SELECT5_OFFSET 0x60000
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#define EVENT_SELECT4_OFFSET 0x50000
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#define EVENT_SELECT3_OFFSET 0x40000
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#define EVENT_SELECT2_OFFSET 0x30000
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#define EVENT_SELECT1_OFFSET 0x20000
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#define EVENT_SELECT0_OFFSET 0x10000
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#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \
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(0x10000 * (index)))
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/* Control and ID register offsets */
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#define CTRL_OVERRIDE_REG 0x0
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#define SECURE_ACCESS_REG 0x8
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#define STATUS_REG 0xc
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#define IMPRECISE_ERR_REG 0x10
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#define PERFMON_CTRL_REG 0x100
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#define IFACE_MON_CTRL_REG 0x104
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/* Component and peripheral ID registers */
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#define PERIPHERAL_ID0 0xFE0
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#define PERIPHERAL_ID1 0xFE4
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#define PERIPHERAL_ID2 0xFE8
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#define PERIPHERAL_ID3 0xFEC
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#define PERIPHERAL_ID4 0xFD0
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#define PERIPHERAL_ID5 0xFD4
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#define PERIPHERAL_ID6 0xFD8
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#define PERIPHERAL_ID7 0xFDC
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#define COMPONENT_ID0 0xFF0
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#define COMPONENT_ID1 0xFF4
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#define COMPONENT_ID2 0xFF8
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#define COMPONENT_ID3 0xFFC
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#define COMPONENT_ID4 0x1000
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#define COMPONENT_ID5 0x1004
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#define COMPONENT_ID6 0x1008
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#define COMPONENT_ID7 0x100C
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/* Slave interface register offsets */
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#define SNOOP_CTRL_REG 0x0
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#define SH_OVERRIDE_REG 0x4
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#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100
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#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104
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#define MAX_OT_REG 0x110
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/* Snoop Control register bit definitions */
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#define DVM_EN_BIT (1 << 1)
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#define SNOOP_EN_BIT (1 << 0)
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#define SUPPORT_SNOOPS (1 << 30)
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#define SUPPORT_DVM (1 << 31)
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/* Status register bit definitions */
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#define CHANGE_PENDING_BIT (1 << 0)
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/* Event and count register offsets */
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#define EVENT_SELECT_REG 0x0
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#define EVENT_COUNT_REG 0x4
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#define COUNT_CNTRL_REG 0x8
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#define COUNT_OVERFLOW_REG 0xC
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/* Slave interface monitor registers */
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#define INT_MON_REG_SI0 0x90000
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#define INT_MON_REG_SI1 0x90004
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#define INT_MON_REG_SI2 0x90008
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#define INT_MON_REG_SI3 0x9000C
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#define INT_MON_REG_SI4 0x90010
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#define INT_MON_REG_SI5 0x90014
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#define INT_MON_REG_SI6 0x90018
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/* Master interface monitor registers */
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#define INT_MON_REG_MI0 0x90100
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#define INT_MON_REG_MI1 0x90104
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#define INT_MON_REG_MI2 0x90108
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#define INT_MON_REG_MI3 0x9010c
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#define INT_MON_REG_MI4 0x90110
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#define INT_MON_REG_MI5 0x90114
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#define SLAVE_IF_UNUSED -1
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#if ARM_CCI_PRODUCT_ID == 400
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#define CCI_SLAVE_INTERFACE_COUNT 5
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#elif ARM_CCI_PRODUCT_ID == 500
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#define CCI_SLAVE_INTERFACE_COUNT 7
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#else
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#error "Invalid CCI product or CCI not supported"
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#endif
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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/* Function declarations */
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/*
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* The ARM CCI driver needs the following:
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* 1. Base address of the CCI-500/CCI-400
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* 2. An array of map between AMBA 4 master ids and ACE/ACE lite slave
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* interfaces.
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* 3. Size of the array.
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*
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* SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists
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* for that interface.
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*/
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void cci_init(uintptr_t cci_base,
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const int *map,
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unsigned int num_cci_masters);
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void cci_enable_snoop_dvm_reqs(unsigned int master_id);
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void cci_disable_snoop_dvm_reqs(unsigned int master_id);
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#endif /* __ASSEMBLY__ */
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#endif /* __CCI_H__ */
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