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103 lines
3.1 KiB
103 lines
3.1 KiB
/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FVP_R_DEF_H
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#define FVP_R_DEF_H
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#include <lib/utils_def.h>
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/******************************************************************************
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* FVP-R topology constants
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*****************************************************************************/
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#define FVP_R_CLUSTER_COUNT 2
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#define FVP_R_MAX_CPUS_PER_CLUSTER 4
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#define FVP_R_MAX_PE_PER_CPU 1
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#define FVP_R_PRIMARY_CPU 0x0
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/******************************************************************************
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* Definition of platform soc id
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*****************************************************************************/
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#define FVP_R_SOC_ID 0
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/*******************************************************************************
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* FVP_R memory map related constants
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******************************************************************************/
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#define FLASH1_BASE UL(0x8c000000)
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#define FLASH1_SIZE UL(0x04000000)
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#define PSRAM_BASE UL(0x94000000)
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#define PSRAM_SIZE UL(0x04000000)
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#define VRAM_BASE UL(0x98000000)
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#define VRAM_SIZE UL(0x02000000)
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/* Aggregate of all devices in the first GB */
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#define DEVICE0_BASE UL(0xa0000000)
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#define DEVICE0_SIZE UL(0x0c200000)
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/*
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* In case of FVP_R models with CCN, the CCN register space overlaps into
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* the NSRAM area.
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*/
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#define DEVICE1_BASE UL(0xae000000)
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#define DEVICE1_SIZE UL(0x1A00000)
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#define NSRAM_BASE UL(0xae000000)
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#define NSRAM_SIZE UL(0x10000)
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/* Devices in the second GB */
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#define DEVICE2_BASE UL(0xffe00000)
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#define DEVICE2_SIZE UL(0x00200000)
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#define PCIE_EXP_BASE UL(0xc0000000)
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#define TZRNG_BASE UL(0x7fe60000)
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/* Non-volatile counters */
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#define TRUSTED_NVCTR_BASE UL(0xffe70000)
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#define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0000))
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#define TFW_NVCTR_SIZE UL(4)
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#define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0004))
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#define NTFW_CTR_SIZE UL(4)
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/* Keys */
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#define SOC_KEYS_BASE UL(0xffe80000)
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#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + UL(0x0000))
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#define TZ_PUB_KEY_HASH_SIZE UL(32)
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#define HU_KEY_BASE (SOC_KEYS_BASE + UL(0x0020))
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#define HU_KEY_SIZE UL(16)
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#define END_KEY_BASE (SOC_KEYS_BASE + UL(0x0044))
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#define END_KEY_SIZE UL(32)
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/* Constants to distinguish FVP_R type */
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#define HBI_BASE_FVP_R U(0x020)
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#define REV_BASE_FVP_R_V0 U(0x0)
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#define REV_BASE_FVP_R_REVC U(0x2)
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#define HBI_FOUNDATION_FVP_R U(0x010)
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#define REV_FOUNDATION_FVP_R_V2_0 U(0x0)
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#define REV_FOUNDATION_FVP_R_V2_1 U(0x1)
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#define REV_FOUNDATION_FVP_R_v9_1 U(0x2)
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#define REV_FOUNDATION_FVP_R_v9_6 U(0x3)
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#define BLD_GIC_VE_MMAP U(0x0)
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#define BLD_GIC_A53A57_MMAP U(0x1)
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#define ARCH_MODEL U(0x1)
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/* FVP_R Power controller base address*/
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#define PWRC_BASE UL(0x1c100000)
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/* FVP_R SP804 timer frequency is 35 MHz*/
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#define SP804_TIMER_CLKMULT 1
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#define SP804_TIMER_CLKDIV 35
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/* SP810 controller. FVP_R specific flags */
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#define FVP_R_SP810_CTRL_TIM0_OV BIT_32(16)
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#define FVP_R_SP810_CTRL_TIM1_OV BIT_32(18)
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#define FVP_R_SP810_CTRL_TIM2_OV BIT_32(20)
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#define FVP_R_SP810_CTRL_TIM3_OV BIT_32(22)
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#endif /* FVP_R_DEF_H */
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