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128 lines
4.0 KiB
128 lines
4.0 KiB
/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <drivers/arm/fvp/fvp_pwrc.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/gicv3.h>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_get_my_entrypoint
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.globl plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* TODO: Should we read the PSYS register to make sure
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* that the request has gone through.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* ---------------------------------------------
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* Power down this cpu.
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* TODO: Do we need to worry about powering the
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* cluster down as well here? That will need
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* locks which we won't have unless an elf-
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* loader zeroes out the zi section.
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* ---------------------------------------------
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*/
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mrs x0, mpidr_el1
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mov_imm x1, PWRC_BASE
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str w0, [x1, #PPOFFR_OFF]
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/* ---------------------------------------------
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* There is no sane reason to come out of this
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* wfi so panic if we do. This cpu will be pow-
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* ered on and reset by the cpu_on pm api
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* ---------------------------------------------
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*/
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dsb sy
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wfi
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no_ret plat_panic_handler
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and warm
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* boot. On FVP_R, this information can be queried from the power
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* controller. The Power Control SYS Status Register (PSYSR) indicates
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* the wake-up reason for the CPU.
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*
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* For a cold boot, return 0.
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* For a warm boot, read the mailbox and return the address it contains.
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*
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* TODO: PSYSR is a common register and should be
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* accessed using locks. Since it is not possible
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* to use locks immediately after a cold reset
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* we are relying on the fact that after a cold
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* reset all cpus will read the same WK field
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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/* ---------------------------------------------------------------------
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* When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC
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* WakeRequest signal" then it is a warm boot.
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* ---------------------------------------------------------------------
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*/
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mrs x2, mpidr_el1
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mov_imm x1, PWRC_BASE
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str w2, [x1, #PSYSR_OFF]
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ldr w2, [x1, #PSYSR_OFF]
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ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
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cmp w2, #WKUP_PPONR
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beq warm_reset
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cmp w2, #WKUP_GICREQ
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beq warm_reset
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/* Cold reset */
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mov x0, #0
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ret
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warm_reset:
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/* ---------------------------------------------------------------------
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* A mailbox is maintained in the trusted SRAM. It is flushed out of the
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* caches after every update using normal memory so it is safe to read
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* it here with SO attributes.
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* ---------------------------------------------------------------------
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*/
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mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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ldr x0, [x0]
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cbz x0, _panic_handler
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ret
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/* ---------------------------------------------------------------------
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* The power controller indicates this is a warm reset but the mailbox
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* is empty. This should never happen!
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* ---------------------------------------------------------------------
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*/
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_panic_handler:
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no_ret plat_panic_handler
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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mov_imm x1, MPIDR_AFFINITY_MASK
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and x0, x0, x1
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cmp x0, #FVP_R_PRIMARY_CPU
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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