arm-trusted-firmware

History

Manoj Kumar de8bc83ee9 n1sdp: add code for DDR ECC enablement and BL33 copy to DDR N1SDP platform supports RDIMMs with ECC capability. To use the ECC capability, the entire DDR memory space has to be zeroed out before enabling the ECC bits in DMC620. Zeroing out several gigabytes of memory from SCP is quite time consuming so functions are added that zeros out the DDR memory from application processor which is much faster compared to SCP. BL33 binary cannot be copied to DDR memory before enabling ECC so this is also done by TF-A from IOFPGA-DDR3 memory to main DDR4 memory after ECC is enabled. Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which the entire DDR space cannot be accessed as DRAM2 starts in base 0x8080000000. So these macros are redefined for all ARM platforms. Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>		5 years ago
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fdts	board/rde1edge: rename sgiclarkh to rde1edge	6 years ago
include	n1sdp: add code for DDR ECC enablement and BL33 copy to DDR	5 years ago
platform.mk	board/rde1edge: rename sgiclarkh to rde1edge	6 years ago
rde1edge_plat.c	board/rde1edge: rename sgiclarkh to rde1edge	6 years ago
rde1edge_security.c	board/rde1edge: rename sgiclarkh to rde1edge	6 years ago