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303 lines
10 KiB
303 lines
10 KiB
/*
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* Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
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*
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* Copyright (c) 2017-2023 Nuvoton Technology Corp.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common/interrupt_props.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <drivers/arm/gic_common.h>
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include <npcm845x_arm_def.h>
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#include <plat/arm/common/smccc_def.h>
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#include <plat/common/common_def.h>
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#define VALUE_TO_STRING(x) #x
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#define VALUE(x) VALUE_TO_STRING(x)
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#define VAR_NAME_VALUE(var) #var "=" VALUE(var)
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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#define PLATFORM_STACK_SIZE 0x400
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#define PLATFORM_CORE_COUNT NPCM845x_PLATFORM_CORE_COUNT
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#define PLATFORM_CLUSTER_COUNT NPCM845x_CLUSTER_COUNT
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#define PLATFORM_MAX_CPU_PER_CLUSTER NPCM845x_MAX_CPU_PER_CLUSTER
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#define PLAT_PRIMARY_CPU NPCM845x_PLAT_PRIMARY_CPU
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#define PLATFORM_SYSTEM_COUNT NPCM845x_SYSTEM_COUNT
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/* Local power state for power domains in Run state. */
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#define PLAT_LOCAL_STATE_RUN U(0)
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/* Local power state for retention. Valid only for CPU power domains */
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#define PLAT_LOCAL_STATE_RET U(1)
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/*
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* Local power state for OFF/power-down. Valid for CPU and cluster power
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* domains.
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*/
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#define PLAT_LOCAL_STATE_OFF U(2)
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE PLAT_LOCAL_STATE_OFF
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#define PLAT_MAX_RET_STATE PLAT_LOCAL_STATE_RET
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
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#define NPCM845x_MAX_PWR_LVL ARM_PWR_LVL1
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/*
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* Macros used to parse state information from State-ID if it is using the
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* recommended encoding for State-ID.
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*/
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#define PLAT_LOCAL_PSTATE_WIDTH 4
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#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
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/*
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* Required ARM standard platform porting definitions
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*/
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#define PLAT_ARM_CLUSTER_COUNT PLATFORM_CLUSTER_COUNT
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL NPCM845x_MAX_PWR_LVL
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#define PLAT_LOCAL_PSTATE_WIDTH 4
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#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
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#ifdef BL32_BASE
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#ifndef CONFIG_TARGET_ARBEL_PALLADIUM
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#define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE
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#else
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#define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE
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#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */
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#define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */
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#endif /* BL32_BASE */
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#define PWR_DOMAIN_AT_MAX_LVL U(1)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 16
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#define PLAT_ARM_MMAP_ENTRIES 17
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#ifdef NPCM845X_DEBUG
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#define MAX_MMAP_REGIONS 8
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#define NPCM845X_TZ1_BASE 0xFFFB0000
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#endif /* NPCM845X_DEBUG */
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#define FIQ_SMP_CALL_SGI 10
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/* (0x00040000) 128 KB, the rest 128K if it is non secured */
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#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00020000)
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#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
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/* UL(0xfffCE000) add calc ARM_TRUSTED_SRAM_BASE */
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#define ARM_SHARED_RAM_BASE (BL31_BASE + 0x00020000 - ARM_SHARED_RAM_SIZE)
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/* The remaining Trusted SRAM is used to load the BL images */
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#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)
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/*
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* PLAT_ARM_TRUSTED_SRAM_SIZE is taken from platform_def.h 0x20000
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* because only half is secured in this specific implementation
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*/
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#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE)
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#if RESET_TO_BL31
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/* Size of Trusted SRAM - the first 4KB of shared memory */
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#define PLAT_ARM_MAX_BL31_SIZE \
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(PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE)
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#else
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/*
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* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE
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* is calculated using the current BL31 PROGBITS debug size plus the sizes
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* of BL2 and BL1-RW
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*/
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#define PLAT_ARM_MAX_BL31_SIZE \
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(PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE)
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#endif /* RESET_TO_BL31 */
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/*
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* Load address of BL33 for this platform port
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*/
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#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x6208000))
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#ifdef NPCM845X_DEBUG
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#define COUNTER_FREQUENCY 0x07735940 /* f/4 = 125MHz */
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#endif /* NPCM845X_DEBUG */
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#define COUNTER_FREQUENCY 0x0EE6B280 /* f/2 = 250MHz */
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#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
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/* GIC parameters */
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/* Base compatible GIC memory map */
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#define NT_GIC_BASE (0xDFFF8000)
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#define BASE_GICD_BASE (NT_GIC_BASE + 0x1000)
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#define BASE_GICC_BASE (NT_GIC_BASE + 0x2000)
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#define BASE_GICR_BASE (NT_GIC_BASE + 0x200000)
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#define BASE_GICH_BASE (NT_GIC_BASE + 0x4000)
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#define BASE_GICV_BASE (NT_GIC_BASE + 0x6000)
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#define DEVICE1_BASE BASE_GICD_BASE
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#define DEVICE1_SIZE 0x7000
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#ifdef NPCM845X_DEBUG
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/* ((BASE_GICR_BASE - BASE_GICD_BASE) + (PLATFORM_CORE_COUNT * 0x20000)) */
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#define ARM_CPU_START_ADDRESS(m) UL(0xf0800e00 + 0x10 + m * 4)
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#endif /* NPCM845X_DEBUG */
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#define PLAT_REG_BASE NPCM845x_REG_BASE
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#define PLAT_REG_SIZE NPCM845x_REG_SIZE
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/* MMU entry for internal (register) space access */
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#define MAP_DEVICE0 \
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MAP_REGION_FLAT(PLAT_REG_BASE, PLAT_REG_SIZE, MT_DEVICE | MT_RW | MT_NS)
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#define MAP_DEVICE1 \
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MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*
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* Define a list of Group 1 Secure and Group 0 interrupt properties
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* as per GICv3 terminology. On a GICv2 system or mode,
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* the lists will be merged and treated as Group 0 interrupts.
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*/
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#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_EDGE)
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#define PLAT_ARM_G0_IRQ_PROPS(grp)
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/* Required for compilation: */
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_ARM_MAX_BL1_RW_SIZE 0 /* UL(0xB000) */
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#if USE_ROMLIB
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
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#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000)
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#else
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
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#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0)
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#endif /* USE_ROMLIB */
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size
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* plus a little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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#define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) * FVP_BL2_ROMLIB_OPTIMIZATION)
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#else
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/* (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) */
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#define PLAT_ARM_MAX_BL2_SIZE 0
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#endif /* TRUSTED_BOARD_BOOT */
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#undef NPCM_PRINT_ONCE
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#ifdef NPCM_PRINT_ONCE
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#define PRINT_ONLY_ONCE
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#pragma message(VAR_NAME_VALUE(ARM_AP_TZC_DRAM1_BASE))
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#pragma message(VAR_NAME_VALUE(BL31_BASE))
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#pragma message(VAR_NAME_VALUE(BL31_LIMIT))
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#pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL31_SIZE))
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#pragma message(VAR_NAME_VALUE(BL32_BASE))
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#pragma message(VAR_NAME_VALUE(BL32_LIMIT))
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#pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL32_SIZE)
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#pragma message(VAR_NAME_VALUE(SPMD_SPM_AT_SEL2_KKO))
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#endif /* NPCM_PRINT_ONCE */
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#define MAX_IO_DEVICES 4
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#define MAX_IO_HANDLES 4
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#define PLAT_ARM_FIP_BASE 0x0
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#define PLAT_ARM_FIP_MAX_SIZE PLAT_ARM_MAX_BL31_SIZE
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#define PLAT_ARM_BOOT_UART_BASE 0xF0000000
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 115200
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#define PLAT_ARM_RUN_UART_BASE 0xF0000000
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ 115200
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#define PLAT_ARM_CRASH_UART_BASE 0xF0000000
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ 115200
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/*
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* Mailbox to control the secondary cores.All secondary cores are held in a wait
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* loop in cold boot. To release them perform the following steps (plus any
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* additional barriers that may be needed):
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*
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* uint64_t *entrypoint = (uint64_t *)PLAT_NPCM_TM_ENTRYPOINT;
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* *entrypoint = ADDRESS_TO_JUMP_TO;
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*
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* uint64_t *mbox_entry = (uint64_t *)PLAT_NPCM_TM_HOLD_BASE;
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* mbox_entry[cpu_id] = PLAT_NPCM_TM_HOLD_BASE;
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*
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* sev();
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*/
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#define PLAT_NPCM_TRUSTED_MAILBOX_BASE ARM_SHARED_RAM_BASE
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/* The secure entry point to be used on warm reset by all CPUs. */
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#define PLAT_NPCM_TM_ENTRYPOINT PLAT_NPCM_TRUSTED_MAILBOX_BASE
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#define PLAT_NPCM_TM_ENTRYPOINT_SIZE ULL(8)
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/* Hold entries for each CPU. */
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#define PLAT_NPCM_TM_HOLD_BASE \
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(PLAT_NPCM_TM_ENTRYPOINT + PLAT_NPCM_TM_ENTRYPOINT_SIZE)
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#define PLAT_NPCM_TM_HOLD_ENTRY_SIZE ULL(8)
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#define PLAT_NPCM_TM_HOLD_SIZE \
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(PLAT_NPCM_TM_HOLD_ENTRY_SIZE * PLATFORM_CORE_COUNT)
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#define PLAT_NPCM_TRUSTED_NOTIFICATION_BASE \
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(PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE)
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#define PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE ULL(8)
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#define PLAT_NPCM_TRUSTED_NOTIFICATION_SIZE \
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(PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE * PLATFORM_CORE_COUNT)
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#define PLAT_NPCM_TRUSTED_MAILBOX_SIZE \
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(PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE + \
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PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE)
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#define PLAT_NPCM_TM_HOLD_STATE_WAIT ULL(0)
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#define PLAT_NPCM_TM_HOLD_STATE_GO ULL(1)
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#define PLAT_NPCM_TM_HOLD_STATE_BSP_OFF ULL(2)
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#define PLAT_NPCM_TM_NOTIFICATION_START ULL(0xAA)
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#define PLAT_NPCM_TM_NOTIFICATION_BR ULL(0xCC)
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#ifdef NPCM845X_DEBUG
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE 0xfffB0000
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#endif /* NPCM845X_DEBUG */
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#endif /* PLATFORM_DEF_H */
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