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126 lines
3.6 KiB
126 lines
3.6 KiB
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <arm_gic.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <cci.h>
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#include <console.h>
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#include <debug.h>
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#include <errno.h>
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#include <gicv2.h>
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#include <hi6220.h>
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#include <hisi_ipc.h>
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#include <hisi_pwrc.h>
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#include <platform_def.h>
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#include "hikey_def.h"
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#include "hikey_private.h"
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/*
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* The next 2 constants identify the extents of the code & RO data region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
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*/
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#define BL31_RO_BASE (unsigned long)(&__RO_START__)
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#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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static entry_point_info_t bl32_ep_info;
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static entry_point_info_t bl33_ep_info;
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/******************************************************************************
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* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
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* interrupts.
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*****************************************************************************/
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const unsigned int g0_interrupt_array[] = {
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IRQ_SEC_PHY_TIMER,
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IRQ_SEC_SGI_0
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};
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/*
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* Ideally `arm_gic_data` structure definition should be a `const` but it is
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* kept as modifiable for overwriting with different GICD and GICC base when
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* running on FVP with VE memory map.
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*/
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gicv2_driver_data_t hikey_gic_data = {
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.gicd_base = PLAT_ARM_GICD_BASE,
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.gicc_base = PLAT_ARM_GICC_BASE,
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.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
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.g0_interrupt_array = g0_interrupt_array,
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};
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static const int cci_map[] = {
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CCI400_SL_IFACE3_CLUSTER_IX,
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CCI400_SL_IFACE4_CLUSTER_IX
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};
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entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
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{
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entry_point_info_t *next_image_info;
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next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
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/* None of the images on this platform can have 0x0 as the entrypoint */
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if (next_image_info->pc)
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return next_image_info;
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return NULL;
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}
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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{
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/* Initialize the console to provide early debug support */
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console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
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/* Initialize CCI driver */
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cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map));
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
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/*
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* Copy BL3-2 and BL3-3 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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bl32_ep_info = *from_bl2->bl32_ep_info;
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bl33_ep_info = *from_bl2->bl33_ep_info;
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}
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void bl31_plat_arch_setup(void)
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{
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hikey_init_mmu_el3(BL31_BASE,
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BL31_LIMIT - BL31_BASE,
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BL31_RO_BASE,
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BL31_RO_LIMIT,
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BL31_COHERENT_RAM_BASE,
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BL31_COHERENT_RAM_LIMIT);
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}
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void bl31_platform_setup(void)
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{
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/* Initialize the GIC driver, cpu and distributor interfaces */
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gicv2_driver_init(&hikey_gic_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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hisi_ipc_init();
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hisi_pwrc_setup();
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}
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void bl31_plat_runtime_setup(void)
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{
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}
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