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79 lines
1.9 KiB
79 lines
1.9 KiB
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <arm_gic.h>
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#include <assert.h>
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#include <bl31.h>
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#include <bl_common.h>
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#include <console.h>
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#include <cortex_a53.h>
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#include <debug.h>
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#include <errno.h>
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#include <generic_delay_timer.h>
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#include <mmio.h>
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#include <plat_arm.h>
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#include <platform.h>
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#include <stddef.h>
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#include <string.h>
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#include "hi3798cv200.h"
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#include "plat_private.h"
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#include "platform_def.h"
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/* Memory ranges for code and RO data sections */
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#define BL31_RO_BASE (unsigned long)(&__RO_START__)
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#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
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/* Memory ranges for coherent memory section */
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#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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static entry_point_info_t bl33_image_ep_info;
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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return &bl33_image_ep_info;
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}
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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{
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console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
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/* Init console for crash report */
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plat_crash_console_init();
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bl33_image_ep_info = *from_bl2->bl33_ep_info;
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}
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void bl31_platform_setup(void)
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{
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/* Init arch timer */
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generic_delay_timer_init();
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/* Init GIC distributor and CPU interface */
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plat_arm_gic_driver_init();
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plat_arm_gic_init();
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}
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void bl31_plat_runtime_setup(void)
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{
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/* do nothing */
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}
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void bl31_plat_arch_setup(void)
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{
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plat_configure_mmu_el3(BL31_RO_BASE,
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(BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
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BL31_RO_BASE,
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BL31_RO_LIMIT,
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BL31_COHERENT_RAM_BASE,
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BL31_COHERENT_RAM_LIMIT);
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INFO("Boot BL33 from 0x%lx for %lu Bytes\n",
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bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2);
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}
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