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129 lines
3.5 KiB
129 lines
3.5 KiB
/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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.globl bl2u_entrypoint
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func bl2u_entrypoint
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/*---------------------------------------------
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* Store the extents of the tzram available to
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* BL2U and other platform specific information
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* for future use. x0 is currently not used.
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* ---------------------------------------------
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*/
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mov x20, x1
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mov x21, x2
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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adr x0, early_exceptions
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msr vbar_el1, x0
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isb
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/* ---------------------------------------------
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* Enable the SError interrupt now that the
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* exception vectors have been setup.
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* ---------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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/* ---------------------------------------------
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* Enable the instruction cache, stack pointer
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* and data access alignment checks and disable
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* speculative loads.
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* ---------------------------------------------
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el1
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orr x0, x0, x1
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bic x0, x0, #SCTLR_DSSBS_BIT
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msr sctlr_el1, x0
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isb
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/* ---------------------------------------------
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* Invalidate the RW memory used by the BL2U
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* image. This includes the data and NOBITS
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* sections. This is done to safeguard against
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* possible corruption of this memory by dirty
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* cache lines in a system cache as a result of
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* use by an earlier boot loader stage.
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* ---------------------------------------------
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*/
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adr x0, __RW_START__
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adr x1, __RW_END__
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sub x1, x1, x0
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bl inv_dcache_range
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/* ---------------------------------------------
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* Zero out NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* ---------------------------------------------
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*/
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adrp x0, __BSS_START__
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add x0, x0, :lo12:__BSS_START__
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adrp x1, __BSS_END__
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add x1, x1, :lo12:__BSS_END__
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sub x1, x1, x0
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bl zeromem
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/* --------------------------------------------
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* Allocate a stack whose memory will be marked
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* as Normal-IS-WBWA when the MMU is enabled.
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* There is no risk of reading stale stack
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* memory after enabling the MMU as only the
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* primary cpu is running at the moment.
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* --------------------------------------------
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*/
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bl plat_set_my_stack
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/* ---------------------------------------------
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* Initialize the stack protector canary before
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* any C code is called.
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* ---------------------------------------------
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*/
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#if STACK_PROTECTOR_ENABLED
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bl update_stack_protector_canary
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#endif
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/* ---------------------------------------------
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* Perform early platform setup & platform
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* specific early arch. setup e.g. mmu setup
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* ---------------------------------------------
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*/
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mov x0, x20
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mov x1, x21
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bl bl2u_early_platform_setup
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bl bl2u_plat_arch_setup
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#if ENABLE_PAUTH
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/* ---------------------------------------------
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* Program APIAKey_EL1
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* and enable pointer authentication.
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* ---------------------------------------------
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*/
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bl pauth_init_enable_el1
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#endif
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/* ---------------------------------------------
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* Jump to bl2u_main function.
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* ---------------------------------------------
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*/
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bl bl2u_main
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/* ---------------------------------------------
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* Should never reach this point.
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* ---------------------------------------------
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*/
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no_ret plat_panic_handler
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endfunc bl2u_entrypoint
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