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55 lines
2.4 KiB
55 lines
2.4 KiB
Runtime Instrumentation Methodology
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===================================
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This document outlines steps for undertaking performance measurements of key
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operations in the Trusted Firmware-A Power State Coordination Interface (PSCI)
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implementation, using the in-built Performance Measurement Framework (PMF) and
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runtime instrumentation timestamps.
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Framework
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~~~~~~~~~
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The tests are based on the ``runtime-instrumentation`` test suite provided by
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the Trusted Firmware Test Framework (TFTF). The release build of this framework
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was used because the results in the debug build became skewed; the console
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output prevented some of the tests from executing in parallel.
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The tests consist of both parallel and sequential tests, which are broadly
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described as follows:
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- **Parallel Tests** This type of test powers on all the non-lead CPUs and
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brings them and the lead CPU to a common synchronization point. The lead CPU
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then initiates the test on all CPUs in parallel.
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- **Sequential Tests** This type of test powers on each non-lead CPU in
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sequence. The lead CPU initiates the test on a non-lead CPU then waits for the
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test to complete before proceeding to the next non-lead CPU. The lead CPU then
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executes the test on itself.
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Note there is very little variance observed in the values given (~1us), although
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the values for each CPU are sometimes interchanged, depending on the order in
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which locks are acquired. Also, there is very little variance observed between
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executing the tests sequentially in a single boot or rebooting between tests.
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Given that runtime instrumentation using PMF is invasive, there is a small
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(unquantified) overhead on the results. PMF uses the generic counter for
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timestamps, which runs at 50MHz on Juno.
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Metrics
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~~~~~~~
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.. glossary::
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Powerdown Latency
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Time taken from entering the TF PSCI implementation to the point the hardware
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enters the low power state (WFI). Referring to the TF runtime instrumentation points, this
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corresponds to: ``(RT_INSTR_ENTER_HW_LOW_PWR - RT_INSTR_ENTER_PSCI)``.
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Wakeup Latency
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Time taken from the point the hardware exits the low power state to exiting
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the TF PSCI implementation. This corresponds to: ``(RT_INSTR_EXIT_PSCI -
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RT_INSTR_EXIT_HW_LOW_PWR)``.
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Cache Flush Latency
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Time taken to flush the caches during powerdown. This corresponds to:
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``(RT_INSTR_EXIT_CFLUSH - RT_INSTR_ENTER_CFLUSH)``.
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