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59 lines
1.9 KiB
59 lines
1.9 KiB
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef PHY_DEFAULT_PORTING_LAYER_H
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#define PHY_DEFAULT_PORTING_LAYER_H
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#define MAX_LANE_NR 6
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#warning "Using default comphy params - you may need to suit them to your board"
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static const struct xfi_params
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xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
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[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
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.g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x5f,
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.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
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.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x1,
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.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
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.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2, .valid = 1
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}
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};
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static const struct sata_params
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sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
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[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
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.g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
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.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
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.g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1,
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.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
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.g3_tx_amp_adj = 0x1,
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.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
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.g3_tx_emph_en = 0x0,
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.g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1,
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.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf,
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.align90 = 0x61,
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.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
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.g3_rx_selmuff = 0x3,
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.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
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.g3_rx_selmufi = 0x3,
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.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
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.g3_rx_selmupf = 0x2,
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.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
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.g3_rx_selmupi = 0x2,
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.polarity_invert = COMPHY_POLARITY_NO_INVERT,
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.valid = 0x1
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},
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};
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static const struct usb_params
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usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
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[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
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.polarity_invert = COMPHY_POLARITY_NO_INVERT
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},
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};
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#endif /* PHY_DEFAULT_PORTING_LAYER_H */
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