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351 lines
7.6 KiB
351 lines
7.6 KiB
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/clock/stm32mp25-clks.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/stm32mp25-resets.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a35";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_msi: clk-msi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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};
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};
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intc: interrupt-controller@4ac00000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x0 0x4ac10000 0x0 0x1000>,
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<0x0 0x4ac20000 0x0 0x2000>,
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<0x0 0x4ac40000 0x0 0x2000>,
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<0x0 0x4ac60000 0x0 0x2000>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&intc>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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always-on;
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges = <0x0 0x0 0x0 0x80000000>;
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rifsc: rifsc@42080000 {
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compatible = "st,stm32mp25-rifsc";
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reg = <0x42080000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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usart2: serial@400e0000 {
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compatible = "st,stm32h7-uart";
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reg = <0x400e0000 0x400>;
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clocks = <&rcc CK_KER_USART2>;
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resets = <&rcc USART2_R>;
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status = "disabled";
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};
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sdmmc1: mmc@48220000 {
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compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00353180>;
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reg = <0x48220000 0x400>, <0x44230400 0x8>;
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clocks = <&rcc CK_KER_SDMMC1>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC1_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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sdmmc2: mmc@48230000 {
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compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00353180>;
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reg = <0x48230000 0x400>, <0x44230800 0x8>;
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clocks = <&rcc CK_KER_SDMMC2>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC2_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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};
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bsec: efuse@44000000 {
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compatible = "st,stm32mp25-bsec";
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reg = <0x44000000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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uid_otp: uid-otp@14 {
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reg = <0x14 0xc>;
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};
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part_number_otp: part-number-otp@24 {
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reg = <0x24 0x4>;
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};
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nand_otp: otp16@40 {
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reg = <0x40 0x4>;
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};
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lifecycle2_otp: otp18@48 {
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reg = <0x48 0x4>;
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};
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nand2_otp: otp20@50 {
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reg = <0x50 0x4>;
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};
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rev_otp@198 {
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reg = <0x198 0x4>;
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};
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package_otp: package-otp@1e8 {
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reg = <0x1e8 0x1>;
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};
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hconf1_otp: otp124@1f0 {
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reg = <0x1f0 0x4>;
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};
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pkh_otp: otp144@240 {
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reg = <0x240 0x20>;
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};
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oem_fip_enc_key: otp260@410 {
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reg = <0x410 0x20>;
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};
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};
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rcc: rcc@44200000 {
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compatible = "st,stm32mp25-rcc";
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reg = <0x44200000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pwr: pwr@44210000 {
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compatible = "st,stm32mp25-pwr";
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reg = <0x44210000 0x400>;
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vddio1: vddio1 {
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regulator-name = "vddio1";
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};
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vddio2: vddio2 {
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regulator-name = "vddio2";
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};
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vddio3: vddio3 {
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regulator-name = "vddio3";
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};
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vddio4: vddio4 {
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regulator-name = "vddio4";
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};
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vddio: vddio {
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regulator-name = "vddio";
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};
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};
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syscfg: syscon@44230000 {
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compatible = "st,stm32mp25-syscfg", "syscon";
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reg = <0x44230000 0x10000>;
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};
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pinctrl: pinctrl@44240000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp257-pinctrl";
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ranges = <0 0x44240000 0xa0400>;
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gpioa: gpio@44240000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc CK_BUS_GPIOA>;
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st,bank-name = "GPIOA";
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status = "disabled";
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};
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gpiob: gpio@44250000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x10000 0x400>;
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clocks = <&rcc CK_BUS_GPIOB>;
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st,bank-name = "GPIOB";
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status = "disabled";
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};
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gpioc: gpio@44260000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x20000 0x400>;
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clocks = <&rcc CK_BUS_GPIOC>;
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st,bank-name = "GPIOC";
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status = "disabled";
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};
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gpiod: gpio@44270000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x30000 0x400>;
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clocks = <&rcc CK_BUS_GPIOD>;
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st,bank-name = "GPIOD";
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status = "disabled";
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};
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gpioe: gpio@44280000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x40000 0x400>;
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clocks = <&rcc CK_BUS_GPIOE>;
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st,bank-name = "GPIOE";
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status = "disabled";
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};
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gpiof: gpio@44290000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x50000 0x400>;
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clocks = <&rcc CK_BUS_GPIOF>;
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st,bank-name = "GPIOF";
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status = "disabled";
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};
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gpiog: gpio@442a0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x60000 0x400>;
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clocks = <&rcc CK_BUS_GPIOG>;
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st,bank-name = "GPIOG";
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status = "disabled";
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};
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gpioh: gpio@442b0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x70000 0x400>;
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clocks = <&rcc CK_BUS_GPIOH>;
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st,bank-name = "GPIOH";
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status = "disabled";
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};
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gpioi: gpio@442c0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x80000 0x400>;
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clocks = <&rcc CK_BUS_GPIOI>;
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st,bank-name = "GPIOI";
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status = "disabled";
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};
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gpioj: gpio@442d0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x90000 0x400>;
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clocks = <&rcc CK_BUS_GPIOJ>;
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st,bank-name = "GPIOJ";
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status = "disabled";
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};
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gpiok: gpio@442e0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xa0000 0x400>;
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clocks = <&rcc CK_BUS_GPIOK>;
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st,bank-name = "GPIOK";
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status = "disabled";
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};
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};
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pinctrl_z: pinctrl@46200000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp257-z-pinctrl";
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ranges = <0 0x46200000 0x400>;
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gpioz: gpio@46200000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x400>;
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clocks = <&rcc CK_BUS_GPIOZ>;
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st,bank-name = "GPIOZ";
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st,bank-ioport = <11>;
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status = "disabled";
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};
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};
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};
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};
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