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202 lines
7.0 KiB
202 lines
7.0 KiB
/*
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* Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#ifndef __ASSEMBLER__
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#include <stdlib.h>
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#endif
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#include <arch.h>
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#include "rcar_def.h"
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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#define FIRMWARE_WELCOME_STR "Booting Rcar-gen3 Trusted Firmware\n"
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/* Size of cacheable stacks */
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#if IMAGE_BL1
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#if TRUSTED_BOARD_BOOT
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#define PLATFORM_STACK_SIZE U(0x1000)
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#else
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#define PLATFORM_STACK_SIZE U(0x440)
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#endif
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#elif IMAGE_BL2
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#if TRUSTED_BOARD_BOOT
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#define PLATFORM_STACK_SIZE U(0x1000)
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#else
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#define PLATFORM_STACK_SIZE U(0x400)
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#endif
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#elif IMAGE_BL31
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#define PLATFORM_STACK_SIZE U(0x800)
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#elif IMAGE_BL32
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#define PLATFORM_STACK_SIZE U(0x440)
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#endif
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#define BL332_IMAGE_ID (NS_BL2U_IMAGE_ID + 1)
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#define BL333_IMAGE_ID (NS_BL2U_IMAGE_ID + 2)
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#define BL334_IMAGE_ID (NS_BL2U_IMAGE_ID + 3)
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#define BL335_IMAGE_ID (NS_BL2U_IMAGE_ID + 4)
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#define BL336_IMAGE_ID (NS_BL2U_IMAGE_ID + 5)
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#define BL337_IMAGE_ID (NS_BL2U_IMAGE_ID + 6)
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#define BL338_IMAGE_ID (NS_BL2U_IMAGE_ID + 7)
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#define BL332_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 8)
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#define BL333_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 9)
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#define BL334_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 10)
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#define BL335_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 11)
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#define BL336_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 12)
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#define BL337_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 13)
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#define BL338_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 14)
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#define BL332_CERT_ID (NS_BL2U_IMAGE_ID + 15)
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#define BL333_CERT_ID (NS_BL2U_IMAGE_ID + 16)
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#define BL334_CERT_ID (NS_BL2U_IMAGE_ID + 17)
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#define BL335_CERT_ID (NS_BL2U_IMAGE_ID + 18)
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#define BL336_CERT_ID (NS_BL2U_IMAGE_ID + 19)
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#define BL337_CERT_ID (NS_BL2U_IMAGE_ID + 20)
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#define BL338_CERT_ID (NS_BL2U_IMAGE_ID + 21)
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/* io drivers id */
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#define FLASH_DEV_ID U(0)
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#define EMMC_DEV_ID U(1)
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/*
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* R-Car H3 Cortex-A57
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* L1:I/48KB(16KBx3way) D/32KB(16KBx2way) L2:2MB(128KBx16way)
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* Cortex-A53
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* L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
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*/
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#define PLATFORM_CACHE_LINE_SIZE 64
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#define PLATFORM_CLUSTER_COUNT U(2)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER1_CORE_COUNT U(4)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
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PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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PLATFORM_CLUSTER_COUNT + 1)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define MAX_IO_DEVICES U(3)
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#define MAX_IO_HANDLES U(4)
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/*
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******************************************************************************
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* BL2 specific defines.
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******************************************************************************
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* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
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* size plus a little space for growth.
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*/
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#define RCAR_SYSRAM_BASE U(0xE6300000)
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#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
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#define BL2_LIMIT U(0xE6320000)
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#else
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#define BL2_LIMIT U(0xE6360000)
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#endif
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#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
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#define BL2_BASE U(0xE6304000)
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#define BL2_IMAGE_LIMIT U(0xE6318000)
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#elif (RCAR_LSI == RCAR_V3M)
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#define BL2_BASE U(0xE6344000)
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#define BL2_IMAGE_LIMIT U(0xE636E800)
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#else
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#define BL2_BASE U(0xE6304000)
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#define BL2_IMAGE_LIMIT U(0xE632E800)
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#endif
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#define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
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/*
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******************************************************************************
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* BL31 specific defines.
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******************************************************************************
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* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL3-1 debug size plus a little space for growth.
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*/
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#define BL31_BASE (RCAR_TRUSTED_SRAM_BASE)
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#define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE + \
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RCAR_TRUSTED_SRAM_SIZE)
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#define RCAR_BL31_LOG_BASE (0x44040000)
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#define RCAR_BL31_SDRAM_BTM (RCAR_BL31_LOG_BASE + 0x14000)
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#define RCAR_BL31_LOG_SIZE (RCAR_BL31_SDRAM_BTM - RCAR_BL31_LOG_BASE)
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#define BL31_SRAM_BASE (DEVICE_SRAM_BASE)
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#define BL31_SRAM_LIMIT (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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#ifndef SPD_NONE
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#define BL32_BASE U(0x44100000)
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#define BL32_SIZE U(0x200000)
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#define BL32_LIMIT (BL32_BASE + BL32_SIZE)
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#endif
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/*******************************************************************************
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* BL33
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******************************************************************************/
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#define BL33_BASE DRAM1_NS_BASE
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#define BL33_COMP_SIZE U(0x200000)
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#define BL33_DECOMP_SIZE (BL33_COMP_SIZE * 32)
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#define BL33_COMP_BASE (BL33_BASE + BL33_DECOMP_SIZE)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#if IMAGE_BL1
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#define MAX_XLAT_TABLES U(2)
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#elif IMAGE_BL2
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#define MAX_XLAT_TABLES U(5)
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#elif IMAGE_BL31
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#define MAX_XLAT_TABLES U(4)
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#elif IMAGE_BL32
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#define MAX_XLAT_TABLES U(3)
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#endif
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#if IMAGE_BL2
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
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#endif
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#define MAX_MMAP_REGIONS (RCAR_MMAP_ENTRIES + RCAR_BL_REGIONS)
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two mailboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT (6)
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/*******************************************************************************
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* Size of the per-cpu data in bytes that should be reserved in the generic
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* per-cpu data structure for the RCAR port.
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******************************************************************************/
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#if !USE_COHERENT_MEM
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#define PLAT_PCPU_DATA_SIZE (2)
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#endif
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#endif /* PLATFORM_DEF_H */
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