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97 lines
3.8 KiB
97 lines
3.8 KiB
fvp_r-Platform Threat Model
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Introduction
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This document provides a threat model for TF-A fvp_r platform.
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Target of Evaluation
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In this threat model, the target of evaluation is the fvp_r platform of Trusted
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Firmware for A-class Processors (TF-A). The fvp_r platform provides limited
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support of AArch64 R-class Processors (v8-R64).
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This is a delta document, only pointing out differences from the general TF-A
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threat-model document, :ref:`Generic Threat Model`
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BL1 Only
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========
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The most fundamental difference between the threat model for the current fvp_r
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implementation compared to the general TF-A threat model, is that fvp_r is
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currently limited to BL1 only. Any threats from the general TF-A threat model
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unrelated to BL1 are therefore not relevant to the fvp_r implementation.
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The fvp_r BL1 implementation directly loads a customer/partner-defined runtime
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system. The threat model for that runtime system, being partner-defined, is
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out-of-scope for this threat-model.
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Relatedly, all exceptions, synchronous and asynchronous, are disabled during BL1
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execution. So, any references to exceptions are not relevant.
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EL3 is Unsupported and All Secure
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=================================
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v8-R64 cores do not support EL3, and (essentially) all operation is defined as
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Secure-mode. Therefore:
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- Any threats regarding NS operation are not relevant.
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- Any mentions of SMCs are also not relevant.
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- Anything otherwise-relevant code running in EL3 is instead run in EL2.
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MPU instead of MMU
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==================
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v8-R64 cores, running in EL2, use an MPU for memory management, rather than an
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MMU. The MPU in the fvp_r implementation is configured to function effectively
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identically with the MMU for the usual BL1 implementation. There are
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memory-map differences, but the MPU configuration is functionally equivalent.
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No AArch32 Support
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==================
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Another substantial difference between v8-A and v8-R64 cores is that v8-R64 does
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not support AArch32. However, this is not believed to have any threat-modeling
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ramifications.
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Threat Assessment
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=================
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For this section, please reference the Threat Assessment under the general TF-A
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threat-model document, :ref:`Generic Threat Model`
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The following threats from that document are still relevant to the fvp_r
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implementation:
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- ID 01: An attacker can mangle firmware images to execute arbitrary code.
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- ID 03: An attacker can use Time-of-Check-Time-of-Use (TOCTOU) attack to
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bypass image authentication during the boot process.
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- ID 04: An attacker with physical access can execute arbitrary image by
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bypassing the signature verification stage using clock- or power-glitching
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techniques.
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- ID 05: Information leak via UART logs such as crashes
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- ID 06: An attacker can read sensitive data and execute arbitrary code
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through the external debug and trace interface.
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- ID 08: Memory corruption due to memory overflows and lack of boundary
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checking when accessing resources could allow an attacker to execute
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arbitrary code, modify some state variable to change the normal flow of
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the program, or leak sensitive.
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- ID 11: Misconfiguration of the Memory Protection Unit (MPU) may allow
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normal world software to access sensitive data or execute arbitrary code.
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Arguably, MPUs having fewer memory regions, there may be a temptation to
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share memory regions, making this a greater threat. However, since the
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fvp_r implementation is limited to BL1, since BL1's regions are fixed,
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and since the MPU configuration is equivalent with that for the fvp
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platform and others, this is not expected to be a concern.
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--------------
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*Copyright (c) 2021, Arm Limited. All rights reserved.*
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