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331 lines
6.1 KiB
331 lines
6.1 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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/dts-v1/;
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#include <dt-bindings/clock/stm32mp13-clksrc.h>
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#include "stm32mp135.dtsi"
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#include "stm32mp13xf.dtsi"
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#include "stm32mp13-ddr3-1x4Gb-1066-binF.dtsi"
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#include "stm32mp13-pinctrl.dtsi"
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/ {
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model = "STMicroelectronics STM32MP135F-DK Discovery Board";
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compatible = "st,stm32mp135f-dk", "st,stm32mp135";
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aliases {
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serial0 = &uart4;
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serial1 = &usart1;
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serial2 = &uart8;
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serial3 = &usart2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@c0000000 {
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device_type = "memory";
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reg = <0xc0000000 0x20000000>;
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};
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vin: vin {
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compatible = "regulator-fixed";
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regulator-name = "vin";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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v3v3_ao: v3v3_ao {
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compatible = "regulator-fixed";
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regulator-name = "v3v3_ao";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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&bsec {
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board_id: board_id@f0 {
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reg = <0xf0 0x4>;
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st,non-secure-otp;
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};
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};
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&cpu0 {
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cpu-supply = <&vddcpu>;
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};
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&hash {
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status = "okay";
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_a>;
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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clock-frequency = <400000>;
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status = "disabled";
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secure-status = "okay";
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pmic: stpmic@33 {
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compatible = "st,stpmic1";
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reg = <0x33>;
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status = "disabled";
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secure-status = "okay";
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regulators {
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compatible = "st,stpmic1-regulators";
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buck1-supply = <&vin>;
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buck2-supply = <&vin>;
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buck3-supply = <&vin>;
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buck4-supply = <&vin>;
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ldo1-supply = <&vin>;
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ldo4-supply = <&vin>;
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ldo5-supply = <&vin>;
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ldo6-supply = <&vin>;
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vref_ddr-supply = <&vin>;
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pwr_sw1-supply = <&bst_out>;
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pwr_sw2-supply = <&v3v3_ao>;
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vddcpu: buck1 {
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regulator-name = "vddcpu";
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regulator-min-microvolt = <1250000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-over-current-protection;
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};
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vdd_ddr: buck2 {
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regulator-name = "vdd_ddr";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-over-current-protection;
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};
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vdd: buck3 {
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regulator-name = "vdd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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st,mask-reset;
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regulator-over-current-protection;
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};
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vddcore: buck4 {
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regulator-name = "vddcore";
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regulator-min-microvolt = <1250000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-over-current-protection;
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};
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vdd_adc: ldo1 {
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regulator-name = "vdd_adc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vdd_usb: ldo4 {
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regulator-name = "vdd_usb";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vdd_sd: ldo5 {
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regulator-name = "vdd_sd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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v1v8_periph: ldo6 {
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regulator-name = "v1v8_periph";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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vref_ddr: vref_ddr {
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regulator-name = "vref_ddr";
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regulator-always-on;
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};
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bst_out: boost {
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regulator-name = "bst_out";
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};
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v3v3_sw: pwr_sw2 {
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regulator-name = "v3v3_sw";
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regulator-active-discharge = <1>;
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regulator-always-on;
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};
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};
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};
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};
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&iwdg2 {
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timeout-sec = <32>;
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status = "okay";
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};
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&pka {
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secure-status = "okay";
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};
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&pwr_regulators {
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vdd-supply = <&vdd>;
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vdd_3v3_usbfs-supply = <&vdd_usb>;
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};
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&rcc {
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MLAHBS_PLL3
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CLK_CKPER_HSE
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CLK_RTC_LSE
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CLK_SDMMC1_PLL4P
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CLK_SDMMC2_PLL4P
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_I2C4_HSI
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CLK_USBO_USBPHY
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CLK_I2C12_HSI
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CLK_UART2_HSI
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CLK_UART4_HSI
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CLK_SAES_AXI
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>;
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st,clkdiv = <
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DIV(DIV_AXI, 0)
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DIV(DIV_MLAHB, 0)
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DIV(DIV_APB1, 1)
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DIV(DIV_APB2, 1)
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DIV(DIV_APB3, 1)
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DIV(DIV_APB4, 1)
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DIV(DIV_APB5, 2)
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DIV(DIV_APB6, 1)
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DIV(DIV_RTC, 0)
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>;
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st,pll_vco {
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pll1_vco_1300Mhz: pll1-vco-1300Mhz {
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src = < CLK_PLL12_HSE >;
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divmn = < 2 80 >;
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frac = < 0x800 >;
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};
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pll2_vco_1066Mhz: pll2-vco-1066Mhz {
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src = < CLK_PLL12_HSE >;
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divmn = < 2 65 >;
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frac = < 0x1400 >;
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};
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pll3_vco_417_8Mhz: pll2-vco-417_8Mhz {
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src = < CLK_PLL3_HSE >;
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divmn = < 1 33 >;
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frac = < 0x1a04 >;
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};
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pll4_vco_600Mhz: pll2-vco-600Mhz {
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src = < CLK_PLL4_HSE >;
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divmn = < 1 49 >;
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};
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};
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/* VCO = 1300.0 MHz => P = 650 (CPU) */
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pll1:st,pll@0 {
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compatible = "st,stm32mp1-pll";
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reg = <0>;
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st,pll = < &pll1_cfg1 >;
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pll1_cfg1: pll1_cfg1 {
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st,pll_vco = < &pll1_vco_1300Mhz >;
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st,pll_div_pqr = < 0 1 1 >;
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};
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};
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */
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pll2:st,pll@1 {
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compatible = "st,stm32mp1-pll";
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reg = <1>;
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st,pll = < &pll2_cfg1 >;
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pll2_cfg1: pll2_cfg1 {
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st,pll_vco = < &pll2_vco_1066Mhz >;
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st,pll_div_pqr = < 1 1 0 >;
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};
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};
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/* VCO = 417.8 MHz => P = 209, Q = 24, R = 209 */
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pll3:st,pll@2 {
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compatible = "st,stm32mp1-pll";
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reg = <2>;
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st,pll = < &pll3_cfg1 >;
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pll3_cfg1: pll3_cfg1 {
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st,pll_vco = < &pll3_vco_417_8Mhz >;
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st,pll_div_pqr = < 1 16 1 >;
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};
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};
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/* VCO = 600.0 MHz => P = 50, Q = 10, R = 100 */
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pll4:st,pll@3 {
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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st,pll = < &pll4_cfg1 >;
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pll4_cfg1: pll4_cfg1 {
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st,pll_vco = < &pll4_vco_600Mhz >;
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st,pll_div_pqr = < 11 59 5 >;
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};
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};
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};
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&rng {
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status = "okay";
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};
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&saes {
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secure-status = "okay";
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};
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&sdmmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
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disable-wp;
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st,neg-edge;
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bus-width = <4>;
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vmmc-supply = <&vdd_sd>;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_pins_a>;
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status = "okay";
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};
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&uart8 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart8_pins_a>;
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status = "disabled";
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};
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&usart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&usart1_pins_a>;
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uart-has-rtscts;
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status = "disabled";
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};
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