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394 lines
8.4 KiB
394 lines
8.4 KiB
/*
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include "qos_init.h"
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#include "qos_common.h"
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#include "qos_reg.h"
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#include "rcar_def.h"
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#if RCAR_LSI == RCAR_AUTO
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#include "H3/qos_init_h3_v10.h"
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#include "H3/qos_init_h3_v11.h"
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#include "H3/qos_init_h3_v20.h"
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#include "H3/qos_init_h3_v30.h"
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#include "M3/qos_init_m3_v10.h"
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#include "M3/qos_init_m3_v11.h"
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#include "M3/qos_init_m3_v30.h"
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#include "M3N/qos_init_m3n_v10.h"
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#include "V3M/qos_init_v3m.h"
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#endif
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#if RCAR_LSI == RCAR_H3 /* H3 */
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#include "H3/qos_init_h3_v10.h"
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#include "H3/qos_init_h3_v11.h"
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#include "H3/qos_init_h3_v20.h"
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#include "H3/qos_init_h3_v30.h"
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#endif
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#if RCAR_LSI == RCAR_H3N /* H3 */
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#include "H3/qos_init_h3n_v30.h"
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#endif
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#if RCAR_LSI == RCAR_M3 /* M3 */
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#include "M3/qos_init_m3_v10.h"
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#include "M3/qos_init_m3_v11.h"
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#include "M3/qos_init_m3_v30.h"
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#endif
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#if RCAR_LSI == RCAR_M3N /* M3N */
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#include "M3N/qos_init_m3n_v10.h"
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#endif
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#if RCAR_LSI == RCAR_V3M /* V3M */
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#include "V3M/qos_init_v3m.h"
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#endif
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#if RCAR_LSI == RCAR_E3 /* E3 */
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#include "E3/qos_init_e3_v10.h"
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#endif
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#if RCAR_LSI == RCAR_D3 /* D3 */
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#include "D3/qos_init_d3.h"
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#endif
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#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
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#define DRAM_CH_CNT 0x04
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uint32_t qos_init_ddr_ch;
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uint8_t qos_init_ddr_phyvalid;
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#endif
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#define PRR_PRODUCT_ERR(reg) \
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do { \
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ERROR("LSI Product ID(PRR=0x%x) QoS " \
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"initialize not supported.\n", reg); \
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panic(); \
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} while (0)
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#define PRR_CUT_ERR(reg) \
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do { \
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ERROR("LSI Cut ID(PRR=0x%x) QoS " \
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"initialize not supported.\n", reg); \
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panic(); \
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} while (0)
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void rcar_qos_init(void)
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{
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uint32_t reg;
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#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
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uint32_t i;
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qos_init_ddr_ch = 0;
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qos_init_ddr_phyvalid = get_boardcnf_phyvalid();
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for (i = 0; i < DRAM_CH_CNT; i++) {
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if ((qos_init_ddr_phyvalid & (1 << i))) {
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qos_init_ddr_ch++;
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}
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}
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#endif
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reg = mmio_read_32(PRR);
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#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
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switch (reg & PRR_PRODUCT_MASK) {
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case PRR_PRODUCT_H3:
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
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switch (reg & PRR_CUT_MASK) {
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case PRR_PRODUCT_10:
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qos_init_h3_v10();
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break;
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case PRR_PRODUCT_11:
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qos_init_h3_v11();
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break;
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case PRR_PRODUCT_20:
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qos_init_h3_v20();
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break;
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case PRR_PRODUCT_30:
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default:
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qos_init_h3_v30();
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break;
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}
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#elif (RCAR_LSI == RCAR_H3N)
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switch (reg & PRR_CUT_MASK) {
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case PRR_PRODUCT_30:
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default:
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qos_init_h3n_v30();
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break;
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}
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#else
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PRR_PRODUCT_ERR(reg);
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#endif
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break;
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case PRR_PRODUCT_M3:
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
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switch (reg & PRR_CUT_MASK) {
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case PRR_PRODUCT_10:
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qos_init_m3_v10();
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break;
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case PRR_PRODUCT_21: /* M3 Cut 13 */
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qos_init_m3_v11();
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break;
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case PRR_PRODUCT_30: /* M3 Cut 30 */
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default:
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qos_init_m3_v30();
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break;
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}
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#else
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PRR_PRODUCT_ERR(reg);
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#endif
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break;
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case PRR_PRODUCT_M3N:
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
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switch (reg & PRR_CUT_MASK) {
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case PRR_PRODUCT_10:
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default:
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qos_init_m3n_v10();
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break;
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}
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#else
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PRR_PRODUCT_ERR(reg);
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#endif
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break;
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case PRR_PRODUCT_V3M:
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M)
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switch (reg & PRR_CUT_MASK) {
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case PRR_PRODUCT_10:
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case PRR_PRODUCT_20:
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default:
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qos_init_v3m();
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break;
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}
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#else
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PRR_PRODUCT_ERR(reg);
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#endif
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break;
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case PRR_PRODUCT_E3:
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#if (RCAR_LSI == RCAR_E3)
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switch (reg & PRR_CUT_MASK) {
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case PRR_PRODUCT_10:
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default:
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qos_init_e3_v10();
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break;
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}
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#else
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PRR_PRODUCT_ERR(reg);
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#endif
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break;
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case PRR_PRODUCT_D3:
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#if (RCAR_LSI == RCAR_D3)
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switch (reg & PRR_CUT_MASK) {
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case PRR_PRODUCT_10:
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default:
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qos_init_d3();
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break;
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}
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#else
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PRR_PRODUCT_ERR(reg);
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#endif
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break;
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default:
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PRR_PRODUCT_ERR(reg);
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break;
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}
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#else
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#if RCAR_LSI == RCAR_H3 /* H3 */
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#if RCAR_LSI_CUT == RCAR_CUT_10
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/* H3 Cut 10 */
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if ((PRR_PRODUCT_H3 | PRR_PRODUCT_10)
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!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_h3_v10();
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#elif RCAR_LSI_CUT == RCAR_CUT_11
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/* H3 Cut 11 */
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if ((PRR_PRODUCT_H3 | PRR_PRODUCT_11)
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!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_h3_v11();
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#elif RCAR_LSI_CUT == RCAR_CUT_20
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/* H3 Cut 20 */
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if ((PRR_PRODUCT_H3 | PRR_PRODUCT_20)
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!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_h3_v20();
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#else
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/* H3 Cut 30 or later */
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if ((PRR_PRODUCT_H3)
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!= (reg & (PRR_PRODUCT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_h3_v30();
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#endif
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#elif RCAR_LSI == RCAR_H3N /* H3 */
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/* H3N Cut 30 or later */
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if ((PRR_PRODUCT_H3)
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!= (reg & (PRR_PRODUCT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_h3n_v30();
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#elif RCAR_LSI == RCAR_M3 /* M3 */
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#if RCAR_LSI_CUT == RCAR_CUT_10
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/* M3 Cut 10 */
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if ((PRR_PRODUCT_M3 | PRR_PRODUCT_10)
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!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_m3_v10();
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#elif RCAR_LSI_CUT == RCAR_CUT_11
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/* M3 Cut 11 */
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if ((PRR_PRODUCT_M3 | PRR_PRODUCT_20)
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!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_m3_v11();
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#elif RCAR_LSI_CUT == RCAR_CUT_13
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/* M3 Cut 13 */
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if ((PRR_PRODUCT_M3 | PRR_PRODUCT_21)
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!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_m3_v11();
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#else
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/* M3 Cut 30 or later */
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if ((PRR_PRODUCT_M3)
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!= (reg & (PRR_PRODUCT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_m3_v30();
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#endif
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#elif RCAR_LSI == RCAR_M3N /* M3N */
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/* M3N Cut 10 or later */
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if ((PRR_PRODUCT_M3N)
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!= (reg & (PRR_PRODUCT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_m3n_v10();
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#elif RCAR_LSI == RCAR_V3M /* V3M */
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/* V3M Cut 10 or later */
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if ((PRR_PRODUCT_V3M)
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!= (reg & (PRR_PRODUCT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_v3m();
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#elif RCAR_LSI == RCAR_D3 /* D3 */
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/* D3 Cut 10 or later */
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if ((PRR_PRODUCT_D3)
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!= (reg & (PRR_PRODUCT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_d3();
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#elif RCAR_LSI == RCAR_E3 /* E3 */
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/* E3 Cut 10 or later */
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if ((PRR_PRODUCT_E3)
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!= (reg & (PRR_PRODUCT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_e3_v10();
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#else
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#error "Don't have QoS initialize routine(Unknown chip)."
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#endif
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#endif
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}
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#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
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uint32_t get_refperiod(void)
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{
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uint32_t refperiod = QOSWT_WTSET0_CYCLE;
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#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
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uint32_t reg;
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reg = mmio_read_32(PRR);
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switch (reg & PRR_PRODUCT_MASK) {
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
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case PRR_PRODUCT_H3:
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switch (reg & PRR_CUT_MASK) {
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case PRR_PRODUCT_10:
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case PRR_PRODUCT_11:
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break;
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case PRR_PRODUCT_20:
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case PRR_PRODUCT_30:
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default:
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refperiod = REFPERIOD_CYCLE;
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break;
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}
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break;
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#elif (RCAR_LSI == RCAR_H3N)
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case PRR_PRODUCT_H3:
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switch (reg & PRR_CUT_MASK) {
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case PRR_PRODUCT_30:
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default:
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refperiod = REFPERIOD_CYCLE;
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break;
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}
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break;
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#endif
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
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case PRR_PRODUCT_M3:
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switch (reg & PRR_CUT_MASK) {
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case PRR_PRODUCT_10:
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break;
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case PRR_PRODUCT_20: /* M3 Cut 11 */
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case PRR_PRODUCT_21: /* M3 Cut 13 */
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case PRR_PRODUCT_30: /* M3 Cut 30 */
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default:
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refperiod = REFPERIOD_CYCLE;
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break;
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}
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break;
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#endif
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
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case PRR_PRODUCT_M3N:
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refperiod = REFPERIOD_CYCLE;
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break;
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#endif
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default:
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break;
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}
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#elif RCAR_LSI == RCAR_H3
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#if RCAR_LSI_CUT == RCAR_CUT_10
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/* H3 Cut 10 */
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#elif RCAR_LSI_CUT == RCAR_CUT_11
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/* H3 Cut 11 */
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#else
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/* H3 Cut 20 */
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/* H3 Cut 30 or later */
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refperiod = REFPERIOD_CYCLE;
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#endif
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#elif RCAR_LSI == RCAR_H3N
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/* H3N Cut 30 or later */
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refperiod = REFPERIOD_CYCLE;
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#elif RCAR_LSI == RCAR_M3
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#if RCAR_LSI_CUT == RCAR_CUT_10
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/* M3 Cut 10 */
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#else
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/* M3 Cut 11 */
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/* M3 Cut 13 */
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/* M3 Cut 30 or later */
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refperiod = REFPERIOD_CYCLE;
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#endif
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#elif RCAR_LSI == RCAR_M3N /* for M3N */
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refperiod = REFPERIOD_CYCLE;
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#endif
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return refperiod;
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}
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#endif
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void rcar_qos_dbsc_setting(struct rcar_gen3_dbsc_qos_settings *qos,
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unsigned int qos_size, bool dbsc_wren)
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{
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int i;
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/* Register write enable */
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if (dbsc_wren)
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io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
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for (i = 0; i < qos_size; i++)
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io_write_32(qos[i].reg, qos[i].val);
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/* Register write protect */
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if (dbsc_wren)
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io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
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}
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