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45 lines
1004 B
45 lines
1004 B
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <dcfg.h>
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#include <lib/mmio.h>
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#include <pmu.h>
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void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr)
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{
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uint32_t *cltbenr = NULL;
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uint32_t cltbenr_val = 0U;
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cltbenr = (uint32_t *)(nxp_pmu_addr
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+ CLUST_TIMER_BASE_ENBL_OFFSET);
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cltbenr_val = mmio_read_32((uintptr_t)cltbenr);
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cltbenr_val = cltbenr_val
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mmio_write_32((uintptr_t)cltbenr, cltbenr_val);
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VERBOSE("Enable cluster time base\n");
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}
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/*
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* Enable core timebase. In certain Layerscape SoCs, the clock for each core's
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* has an enable bit in the PMU Physical Core Time Base Enable
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* Register (PCTBENR), which allows the watchdog to operate.
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*/
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void enable_core_tb(uintptr_t nxp_pmu_addr)
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{
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uint32_t *pctbenr = (uint32_t *) (nxp_pmu_addr +
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CORE_TIMEBASE_ENBL_OFFSET);
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mmio_write_32((uintptr_t)pctbenr, 0xff);
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}
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