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689 lines
16 KiB
689 lines
16 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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nvmem-cells = <&part_number_otp>;
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nvmem-cell-names = "part_number";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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intc: interrupt-controller@a0021000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xa0021000 0x1000>,
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<0xa0022000 0x2000>;
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_csi: clk-csi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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timers12: timer@40006000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40006000 0x400>;
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clocks = <&rcc TIM12_K>;
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clock-names = "int";
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status = "disabled";
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};
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usart2: serial@4000e000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4000e000 0x400>;
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interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc USART2_K>;
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resets = <&rcc USART2_R>;
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status = "disabled";
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};
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usart3: serial@4000f000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4000f000 0x400>;
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interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc USART3_K>;
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resets = <&rcc USART3_R>;
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status = "disabled";
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};
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uart4: serial@40010000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40010000 0x400>;
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interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc UART4_K>;
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resets = <&rcc UART4_R>;
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wakeup-source;
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status = "disabled";
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};
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uart5: serial@40011000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40011000 0x400>;
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interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc UART5_K>;
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resets = <&rcc UART5_R>;
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status = "disabled";
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};
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i2c2: i2c@40013000 {
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compatible = "st,stm32mp15-i2c";
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reg = <0x40013000 0x400>;
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interrupt-names = "event", "error";
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interrupts = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc I2C2_K>;
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resets = <&rcc I2C2_R>;
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#address-cells = <1>;
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#size-cells = <0>;
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st,syscfg-fmp = <&syscfg 0x4 0x2>;
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wakeup-source;
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status = "disabled";
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};
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uart7: serial@40018000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40018000 0x400>;
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interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc UART7_K>;
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resets = <&rcc UART7_R>;
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status = "disabled";
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};
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uart8: serial@40019000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40019000 0x400>;
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interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc UART8_K>;
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resets = <&rcc UART8_R>;
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status = "disabled";
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};
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usart6: serial@44003000 {
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compatible = "st,stm32h7-uart";
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reg = <0x44003000 0x400>;
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interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc USART6_K>;
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resets = <&rcc USART6_R>;
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status = "disabled";
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};
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timers15: timer@44006000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x44006000 0x400>;
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clocks = <&rcc TIM15_K>;
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clock-names = "int";
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status = "disabled";
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};
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usbotg_hs: usb-otg@49000000 {
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compatible = "st,stm32mp15-hsotg", "snps,dwc2";
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reg = <0x49000000 0x10000>;
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clocks = <&rcc USBO_K>;
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clock-names = "otg";
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resets = <&rcc USBO_R>;
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reset-names = "dwc2";
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interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
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g-rx-fifo-size = <512>;
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g-np-tx-fifo-size = <32>;
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g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
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dr_mode = "otg";
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usb33d-supply = <&usb33>;
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status = "disabled";
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};
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rcc: rcc@50000000 {
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compatible = "st,stm32mp1-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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secure-interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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secure-interrupt-names = "wakeup";
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};
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pwr_regulators: pwr@50001000 {
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compatible = "st,stm32mp1,pwr-reg";
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reg = <0x50001000 0x10>;
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st,tzcr = <&rcc 0x0 0x1>;
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reg11: reg11 {
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regulator-name = "reg11";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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};
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reg18: reg18 {
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regulator-name = "reg18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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usb33: usb33 {
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regulator-name = "usb33";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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pwr_mcu: pwr_mcu@50001014 {
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compatible = "st,stm32mp151-pwr-mcu", "syscon";
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reg = <0x50001014 0x4>;
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};
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pwr_irq: pwr@50001020 {
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compatible = "st,stm32mp1-pwr";
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reg = <0x50001020 0x100>;
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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exti: interrupt-controller@5000d000 {
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compatible = "st,stm32mp1-exti", "syscon";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000d000 0x400>;
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/* exti_pwr is an extra interrupt controller used for
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* EXTI 55 to 60. It's mapped on pwr interrupt
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* controller.
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*/
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exti_pwr: exti-pwr {
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&pwr_irq>;
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st,irq-number = <6>;
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};
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};
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syscfg: syscon@50020000 {
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compatible = "st,stm32mp157-syscfg", "syscon";
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reg = <0x50020000 0x400>;
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clocks = <&rcc SYSCFG>;
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};
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hash1: hash@54002000 {
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compatible = "st,stm32f756-hash";
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reg = <0x54002000 0x400>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc HASH1>;
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resets = <&rcc HASH1_R>;
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status = "disabled";
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};
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rng1: rng@54003000 {
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compatible = "st,stm32-rng";
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reg = <0x54003000 0x400>;
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clocks = <&rcc RNG1_K>;
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resets = <&rcc RNG1_R>;
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status = "disabled";
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};
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fmc: memory-controller@58002000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "st,stm32mp1-fmc2-ebi";
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reg = <0x58002000 0x1000>;
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clocks = <&rcc FMC_K>;
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resets = <&rcc FMC_R>;
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status = "disabled";
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ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
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<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
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<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
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<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
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<4 0 0x80000000 0x10000000>; /* NAND */
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nand-controller@4,0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32mp1-fmc2-nfc";
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reg = <4 0x00000000 0x1000>,
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<4 0x08010000 0x1000>,
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<4 0x08020000 0x1000>,
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<4 0x01000000 0x1000>,
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<4 0x09010000 0x1000>,
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<4 0x09020000 0x1000>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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qspi: spi@58003000 {
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compatible = "st,stm32f469-qspi";
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reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
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reg-names = "qspi", "qspi_mm";
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc QSPI_K>;
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resets = <&rcc QSPI_R>;
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status = "disabled";
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};
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sdmmc1: mmc@58005000 {
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compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00253180>;
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reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&rcc SDMMC1_K>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC1_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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sdmmc2: mmc@58007000 {
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compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00253180>;
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reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&rcc SDMMC2_K>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC2_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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iwdg2: watchdog@5a002000 {
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compatible = "st,stm32mp1-iwdg";
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reg = <0x5a002000 0x400>;
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secure-interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
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clock-names = "pclk", "lsi";
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status = "disabled";
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};
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ddr: ddr@5a003000 {
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compatible = "st,stm32mp1-ddr";
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reg = <0x5A003000 0x550 0x5A004000 0x234>;
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clocks = <&rcc AXIDCG>,
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<&rcc DDRC1>,
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<&rcc DDRC2>,
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<&rcc DDRPHYC>,
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<&rcc DDRCAPB>,
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<&rcc DDRPHYCAPB>;
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clock-names = "axidcg",
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"ddrc1",
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"ddrc2",
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"ddrphyc",
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"ddrcapb",
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"ddrphycapb";
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status = "okay";
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};
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usbphyc: usbphyc@5a006000 {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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compatible = "st,stm32mp1-usbphyc";
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reg = <0x5a006000 0x1000>;
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clocks = <&rcc USBPHY_K>;
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resets = <&rcc USBPHY_R>;
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vdda1v1-supply = <®11>;
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vdda1v8-supply = <®18>;
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status = "disabled";
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usbphyc_port0: usb-phy@0 {
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#phy-cells = <0>;
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reg = <0>;
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};
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usbphyc_port1: usb-phy@1 {
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#phy-cells = <1>;
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reg = <1>;
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};
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};
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usart1: serial@5c000000 {
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compatible = "st,stm32h7-uart";
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reg = <0x5c000000 0x400>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc USART1_K>;
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resets = <&rcc USART1_R>;
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status = "disabled";
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};
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spi6: spi@5c001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32h7-spi";
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reg = <0x5c001000 0x400>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc SPI6_K>;
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resets = <&rcc SPI6_R>;
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status = "disabled";
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};
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i2c4: i2c@5c002000 {
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compatible = "st,stm32mp15-i2c";
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reg = <0x5c002000 0x400>;
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interrupt-names = "event", "error";
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interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc I2C4_K>;
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resets = <&rcc I2C4_R>;
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#address-cells = <1>;
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#size-cells = <0>;
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st,syscfg-fmp = <&syscfg 0x4 0x8>;
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wakeup-source;
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status = "disabled";
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};
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iwdg1: watchdog@5c003000 {
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compatible = "st,stm32mp1-iwdg";
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reg = <0x5C003000 0x400>;
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interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
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clock-names = "pclk", "lsi";
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status = "disabled";
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};
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rtc: rtc@5c004000 {
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compatible = "st,stm32mp1-rtc";
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reg = <0x5c004000 0x400>;
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clocks = <&rcc RTCAPB>, <&rcc RTC>;
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clock-names = "pclk", "rtc_ck";
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interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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bsec: efuse@5c005000 {
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compatible = "st,stm32mp15-bsec";
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reg = <0x5c005000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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cfg0_otp: cfg0_otp@0 {
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reg = <0x0 0x1>;
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};
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part_number_otp: part_number_otp@4 {
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reg = <0x4 0x1>;
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};
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monotonic_otp: monotonic_otp@10 {
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reg = <0x10 0x4>;
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};
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nand_otp: nand_otp@24 {
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reg = <0x24 0x4>;
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};
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uid_otp: uid_otp@34 {
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reg = <0x34 0xc>;
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};
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package_otp: package_otp@40 {
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reg = <0x40 0x4>;
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};
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hw2_otp: hw2_otp@48 {
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reg = <0x48 0x4>;
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};
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ts_cal1: calib@5c {
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reg = <0x5c 0x2>;
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};
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ts_cal2: calib@5e {
|
|
reg = <0x5e 0x2>;
|
|
};
|
|
pkh_otp: pkh_otp@60 {
|
|
reg = <0x60 0x20>;
|
|
};
|
|
mac_addr: mac_addr@e4 {
|
|
reg = <0xe4 0x8>;
|
|
st,non-secure-otp;
|
|
};
|
|
};
|
|
|
|
etzpc: etzpc@5c007000 {
|
|
compatible = "st,stm32-etzpc";
|
|
reg = <0x5C007000 0x400>;
|
|
clocks = <&rcc TZPC>;
|
|
};
|
|
|
|
stgen: stgen@5c008000 {
|
|
compatible = "st,stm32-stgen";
|
|
reg = <0x5C008000 0x1000>;
|
|
};
|
|
|
|
i2c6: i2c@5c009000 {
|
|
compatible = "st,stm32mp15-i2c";
|
|
reg = <0x5c009000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc I2C6_K>;
|
|
resets = <&rcc I2C6_R>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
st,syscfg-fmp = <&syscfg 0x4 0x20>;
|
|
wakeup-source;
|
|
status = "disabled";
|
|
};
|
|
|
|
tamp: tamp@5c00a000 {
|
|
compatible = "st,stm32-tamp", "simple-bus", "syscon", "simple-mfd";
|
|
reg = <0x5c00a000 0x400>;
|
|
secure-interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc RTCAPB>;
|
|
};
|
|
|
|
/*
|
|
* Break node order to solve dependency probe issue between
|
|
* pinctrl and exti.
|
|
*/
|
|
pinctrl: pinctrl@50002000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "st,stm32mp157-pinctrl";
|
|
ranges = <0 0x50002000 0xa400>;
|
|
interrupt-parent = <&exti>;
|
|
st,syscfg = <&exti 0x60 0xff>;
|
|
pins-are-numbered;
|
|
|
|
gpioa: gpio@50002000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x0 0x400>;
|
|
clocks = <&rcc GPIOA>;
|
|
st,bank-name = "GPIOA";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiob: gpio@50003000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x1000 0x400>;
|
|
clocks = <&rcc GPIOB>;
|
|
st,bank-name = "GPIOB";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioc: gpio@50004000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x2000 0x400>;
|
|
clocks = <&rcc GPIOC>;
|
|
st,bank-name = "GPIOC";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiod: gpio@50005000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x3000 0x400>;
|
|
clocks = <&rcc GPIOD>;
|
|
st,bank-name = "GPIOD";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioe: gpio@50006000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x4000 0x400>;
|
|
clocks = <&rcc GPIOE>;
|
|
st,bank-name = "GPIOE";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiof: gpio@50007000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x5000 0x400>;
|
|
clocks = <&rcc GPIOF>;
|
|
st,bank-name = "GPIOF";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiog: gpio@50008000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x6000 0x400>;
|
|
clocks = <&rcc GPIOG>;
|
|
st,bank-name = "GPIOG";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioh: gpio@50009000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x7000 0x400>;
|
|
clocks = <&rcc GPIOH>;
|
|
st,bank-name = "GPIOH";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioi: gpio@5000a000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x8000 0x400>;
|
|
clocks = <&rcc GPIOI>;
|
|
st,bank-name = "GPIOI";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioj: gpio@5000b000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x9000 0x400>;
|
|
clocks = <&rcc GPIOJ>;
|
|
st,bank-name = "GPIOJ";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiok: gpio@5000c000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0xa000 0x400>;
|
|
clocks = <&rcc GPIOK>;
|
|
st,bank-name = "GPIOK";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pinctrl_z: pinctrl@54004000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "st,stm32mp157-z-pinctrl";
|
|
ranges = <0 0x54004000 0x400>;
|
|
pins-are-numbered;
|
|
interrupt-parent = <&exti>;
|
|
st,syscfg = <&exti 0x60 0xff>;
|
|
|
|
gpioz: gpio@54004000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0 0x400>;
|
|
clocks = <&rcc GPIOZ>;
|
|
st,bank-name = "GPIOZ";
|
|
st,bank-ioport = <11>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|