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172 lines
3.5 KiB
172 lines
3.5 KiB
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <platform_def.h>
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#define LIT_CAPACITY 239
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#define MID_CAPACITY 686
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#define BIG_CAPACITY 1024
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#define MHU_TX_ADDR 46040000 /* hex */
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#define MHU_TX_COMPAT "arm,mhuv3"
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#define MHU_TX_INT_NAME ""
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#define MHU_RX_ADDR 46140000 /* hex */
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#define MHU_RX_COMPAT "arm,mhuv3"
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#define MHU_OFFSET 0x10000
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#define MHU_MBOX_CELLS 3
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#define MHU_RX_INT_NUM 300
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#define MHU_RX_INT_NAME "combined-mbx"
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#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
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#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu"
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#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu"
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#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
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#define UARTCLK_FREQ 3750000
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#if TARGET_FLAVOUR_FVP
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#define DPU_ADDR 4000000000
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#define DPU_IRQ 579
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#elif TARGET_FLAVOUR_FPGA
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#define DPU_ADDR 2cc00000
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#define DPU_IRQ 69
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#endif
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#include "tc-common.dtsi"
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#if TARGET_FLAVOUR_FVP
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#include "tc-fvp.dtsi"
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#else
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#include "tc-fpga.dtsi"
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#endif /* TARGET_FLAVOUR_FVP */
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#include "tc-base.dtsi"
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/ {
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cpus {
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CPU2:cpu@200 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU3:cpu@300 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU6:cpu@600 {
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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};
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CPU7:cpu@700 {
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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};
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};
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cs-pmu@0 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
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};
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cs-pmu@1 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
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};
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cs-pmu@2 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
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};
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cs-pmu@3 {
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compatible = "arm,coresight-pmu";
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reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
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};
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spe-pmu-mid {
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status = "okay";
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};
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spe-pmu-big {
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status = "okay";
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};
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dsu-pmu {
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compatible = "arm,dsu-pmu";
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cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
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};
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ni-pmu {
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compatible = "arm,ni-tower";
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reg = <0x0 0x4f000000 0x0 0x4000000>;
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};
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sram: sram@6000000 {
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cpu_scp_scmi_p2a: scp-shmem@80 {
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compatible = "arm,scmi-shmem";
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reg = <0x80 0x80>;
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};
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};
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firmware {
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scmi {
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mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
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shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
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};
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};
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gic: interrupt-controller@GIC_CTRL_ADDR {
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ppi-partitions {
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ppi_partition_little: interrupt-partition-0 {
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affinity = <&CPU0>, <&CPU1>;
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};
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ppi_partition_mid: interrupt-partition-1 {
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affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
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};
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ppi_partition_big: interrupt-partition-2 {
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affinity = <&CPU6>, <&CPU7>;
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};
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};
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};
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#if TARGET_FLAVOUR_FVP
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smmu_700: iommu@3f000000 {
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status = "okay";
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};
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smmu_700_dpu: iommu@4002a00000 {
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status = "okay";
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};
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#else
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smmu_600: smmu@2ce00000 {
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status = "okay";
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};
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#endif
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dp0: display@DPU_ADDR {
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#if TARGET_FLAVOUR_FVP
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iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
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<&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
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#else /* TARGET_FLAVOUR_FPGA */
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iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>,
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<&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>,
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<&smmu_600 8>, <&smmu_600 9>;
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#endif
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};
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gpu: gpu@2d000000 {
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#if TARGET_FLAVOUR_FVP
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iommus = <&smmu_700 0x200>;
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#endif
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};
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};
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