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120 lines
2.5 KiB
120 lines
2.5 KiB
/*
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* Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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.global enable_mmu_direct_svc_mon
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.global enable_mmu_direct_hyp
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/* void enable_mmu_direct_svc_mon(unsigned int flags) */
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func enable_mmu_direct_svc_mon
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/* Assert that MMU is turned off */
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#if ENABLE_ASSERTIONS
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ldcopr r1, SCTLR
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tst r1, #SCTLR_M_BIT
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ASM_ASSERT(eq)
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#endif
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/* Invalidate TLB entries */
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TLB_INVALIDATE(r0, TLBIALL)
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mov r3, r0
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ldr r0, =mmu_cfg_params
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/* MAIR0. Only the lower 32 bits are used. */
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ldr r1, [r0, #(MMU_CFG_MAIR << 3)]
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stcopr r1, MAIR0
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/* TTBCR. Only the lower 32 bits are used. */
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ldr r2, [r0, #(MMU_CFG_TCR << 3)]
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stcopr r2, TTBCR
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/* TTBR0 */
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ldr r1, [r0, #(MMU_CFG_TTBR0 << 3)]
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ldr r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)]
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stcopr16 r1, r2, TTBR0_64
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/* TTBR1 is unused right now; set it to 0. */
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mov r1, #0
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mov r2, #0
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stcopr16 r1, r2, TTBR1_64
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/*
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* Ensure all translation table writes have drained into memory, the TLB
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* invalidation is complete, and translation register writes are
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* committed before enabling the MMU
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*/
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dsb ish
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isb
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/* Enable enable MMU by honoring flags */
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ldcopr r1, SCTLR
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ldr r2, =(SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT)
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orr r1, r1, r2
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/* Clear C bit if requested */
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tst r3, #DISABLE_DCACHE
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bicne r1, r1, #SCTLR_C_BIT
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stcopr r1, SCTLR
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isb
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bx lr
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endfunc enable_mmu_direct_svc_mon
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/* void enable_mmu_direct_hyp(unsigned int flags) */
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func enable_mmu_direct_hyp
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/* Assert that MMU is turned off */
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#if ENABLE_ASSERTIONS
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ldcopr r1, HSCTLR
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tst r1, #HSCTLR_M_BIT
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ASM_ASSERT(eq)
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#endif
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/* Invalidate TLB entries */
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TLB_INVALIDATE(r0, TLBIALL)
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mov r3, r0
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ldr r0, =mmu_cfg_params
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/* HMAIR0 */
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ldr r1, [r0, #(MMU_CFG_MAIR << 3)]
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stcopr r1, HMAIR0
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/* HTCR */
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ldr r2, [r0, #(MMU_CFG_TCR << 3)]
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stcopr r2, HTCR
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/* HTTBR */
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ldr r1, [r0, #(MMU_CFG_TTBR0 << 3)]
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ldr r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)]
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stcopr16 r1, r2, HTTBR_64
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/*
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* Ensure all translation table writes have drained into memory, the TLB
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* invalidation is complete, and translation register writes are
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* committed before enabling the MMU
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*/
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dsb ish
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isb
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/* Enable enable MMU by honoring flags */
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ldcopr r1, HSCTLR
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ldr r2, =(HSCTLR_WXN_BIT | HSCTLR_C_BIT | HSCTLR_M_BIT)
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orr r1, r1, r2
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/* Clear C bit if requested */
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tst r3, #DISABLE_DCACHE
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bicne r1, r1, #HSCTLR_C_BIT
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stcopr r1, HSCTLR
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isb
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bx lr
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endfunc enable_mmu_direct_hyp
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