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246 lines
4.4 KiB
246 lines
4.4 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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/dts-v1/;
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#include "stm32mp157c.dtsi"
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#include "stm32mp157caa-pinctrl.dtsi"
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/ {
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model = "STMicroelectronics STM32MP157C-ED1 pmic eval daughter";
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compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
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chosen {
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bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram";
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stdout-path = "serial3:115200n8";
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};
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_a>;
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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status = "okay";
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pmic: stpmu1@33 {
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compatible = "st,stpmu1";
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reg = <0x33>;
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status = "okay";
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st,main_control_register = <0x04>;
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st,vin_control_register = <0xc0>;
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st,usb_control_register = <0x30>;
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regulators {
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compatible = "st,stpmu1-regulators";
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v3v3: buck4 {
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regulator-name = "v3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-over-current-protection;
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regulator-initial-mode = <8>;
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regulator-state-standby {
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regulator-suspend-microvolt = <3300000>;
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regulator-unchanged-in-suspend;
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regulator-mode = <8>;
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};
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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regulator-state-disk {
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regulator-off-in-suspend;
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};
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};
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vdd_sd: ldo5 {
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regulator-name = "vdd_sd";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <2900000>;
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regulator-boot-on;
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regulator-state-standby {
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regulator-suspend-microvolt = <2900000>;
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regulator-unchanged-in-suspend;
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};
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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regulator-state-disk {
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regulator-off-in-suspend;
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};
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};
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};
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};
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};
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&iwdg2 {
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instance = <2>;
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timeout-sec = <32>;
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status = "okay";
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};
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&rng1 {
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status = "okay";
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};
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&sdmmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
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broken-cd;
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st,dirpol;
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st,negedge;
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st,pin-ckin;
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bus-width = <4>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-ddr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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&sdmmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
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non-removable;
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no-sd;
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no-sdio;
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st,dirpol;
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st,negedge;
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bus-width = <8>;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_pins_a>;
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resets = <&rcc UART4_R>;
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status = "okay";
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};
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/* ATF Specific */
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
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/ {
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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gpio25 = &gpioz;
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i2c3 = &i2c4;
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};
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soc {
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stgen: stgen@5C008000 {
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compatible = "st,stm32-stgen";
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reg = <0x5C008000 0x1000>;
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status = "okay";
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};
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};
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};
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/* CLOCK init */
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&rcc {
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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>;
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st,pkcs = <
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_DISABLED
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CLK_SDMMC12_PLL3R
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
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CLK_SPI45_HSI
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CLK_SPI6_HSI
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CLK_I2C46_HSI
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CLK_SDMMC3_PLL3R
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CLK_USBO_USBPHY
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CLK_ADC_CKPER
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CLK_CEC_LSE
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CLK_I2C12_HSI
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CLK_I2C35_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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CLK_UART35_HSI
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL3Q
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CLK_FDCAN_PLL4Q
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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CLK_SAI4_PLL3Q
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CLK_RNG1_CSI
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CLK_RNG2_CSI
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CLK_LPTIM1_PCLK1
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CLK_LPTIM23_PCLK3
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CLK_LPTIM45_PCLK3
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>;
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/* VCO = 1300.0 MHz => P = 650 (CPU) */
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pll1: st,pll@0 {
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cfg = < 2 80 0 0 0 PQR(1,0,0) >;
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frac = < 0x800 >;
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};
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
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pll2: st,pll@1 {
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cfg = < 2 65 1 0 0 PQR(1,1,1) >;
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frac = < 0x1400 >;
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};
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/* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */
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pll3: st,pll@2 {
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cfg = < 2 97 3 15 7 PQR(1,1,1) >;
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frac = < 0x9ba >;
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};
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/* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
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pll4: st,pll@3 {
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cfg = < 5 126 8 8 8 PQR(1,1,1) >;
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};
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};
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/delete-node/ &clk_csi;
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