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51 lines
1.4 KiB
51 lines
1.4 KiB
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <cortex_a55.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a55_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A55_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK
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msr CORTEX_A55_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a55_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides cortex_a55 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a55_regs, "aS"
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cortex_a55_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a55_cpu_reg_dump
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adr x6, cortex_a55_regs
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mrs x8, CORTEX_A55_CPUECTLR_EL1
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ret
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endfunc cortex_a55_cpu_reg_dump
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declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \
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CPU_NO_RESET_FUNC, \
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cortex_a55_core_pwr_dwn
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