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86 lines
5.0 KiB
86 lines
5.0 KiB
Advisory TFV-3 (CVE-2017-7563)
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==============================
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+----------------+-------------------------------------------------------------+
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| Title | RO memory is always executable at AArch64 Secure EL1 |
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+================+=============================================================+
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| CVE ID | `CVE-2017-7563`_ |
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+----------------+-------------------------------------------------------------+
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| Date | 06 Apr 2017 |
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+----------------+-------------------------------------------------------------+
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| Versions | v1.3 (since `Pull Request #662`_) |
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| Affected | |
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+----------------+-------------------------------------------------------------+
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| Configurations | AArch64 BL2, TSP or other users of xlat_tables library |
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| Affected | executing at AArch64 Secure EL1 |
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+----------------+-------------------------------------------------------------+
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| Impact | Unexpected Privilege Escalation |
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+----------------+-------------------------------------------------------------+
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| Fix Version | `Pull Request #924`_ |
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+----------------+-------------------------------------------------------------+
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| Credit | ARM |
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+----------------+-------------------------------------------------------------+
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The translation table library in ARM Trusted Firmware (TF) (under
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``lib/xlat_tables`` and ``lib/xlat_tables_v2``) provides APIs to help program
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translation tables in the MMU. The xlat\_tables client specifies its required
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memory mappings in the form of ``mmap_region`` structures. Each ``mmap_region``
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has memory attributes represented by the ``mmap_attr_t`` enumeration type. This
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contains flags to control data access permissions (``MT_RO``/``MT_RW``) and
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instruction execution permissions (``MT_EXECUTE``/``MT_EXECUTE_NEVER``). Thus a
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mapping specifying both ``MT_RO`` and ``MT_EXECUTE_NEVER`` should result in a
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Read-Only (RO), non-executable memory region.
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This feature does not work correctly for AArch64 images executing at Secure EL1.
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Any memory region mapped as RO will always be executable, regardless of whether
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the client specified ``MT_EXECUTE`` or ``MT_EXECUTE_NEVER``.
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The vulnerability is known to affect the BL2 and Test Secure Payload (TSP)
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images on platforms that enable the ``SEPARATE_CODE_AND_RODATA`` build option,
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which includes all ARM standard platforms, and the upstream Xilinx and NVidia
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platforms. The RO data section for these images on these platforms is
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unexpectedly executable instead of non-executable. Other platforms or
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``xlat_tables`` clients may also be affected.
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The vulnerability primarily manifests itself after `Pull Request #662`_. Before
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that, ``xlat_tables`` clients could not specify instruction execution
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permissions separately to data access permissions. All RO normal memory regions
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were implicitly executable. Before `Pull Request #662`_. the vulnerability
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would only manifest itself for device memory mapped as RO; use of this mapping
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is considered rare, although the upstream QEMU platform uses this mapping when
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the ``DEVICE2_BASE`` build option is used.
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Note that one or more separate vulnerabilities are also required to exploit this
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vulnerability.
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The vulnerability is due to incorrect handling of the execute-never bits in the
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translation tables. The EL3 translation regime uses a single ``XN`` bit to
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determine whether a region is executable. The Secure EL1&0 translation regime
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handles 2 Virtual Address (VA) ranges and so uses 2 bits, ``UXN`` and ``PXN``.
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The ``xlat_tables`` library only handles the ``XN`` bit, which maps to ``UXN``
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in the Secure EL1&0 regime. As a result, this programs the Secure EL0 execution
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permissions but always leaves the memory as executable at Secure EL1.
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The vulnerability is mitigated by the following factors:
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- The xlat\_tables library ensures that all Read-Write (RW) memory regions are
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non-executable by setting the ``SCTLR_ELx.WXN`` bit. This overrides any value
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of the ``XN``, ``UXN`` or ``PXN`` bits in the translation tables. See the
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``enable_mmu()`` function:
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::
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sctlr = read_sctlr_el##_el(); \
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
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- AArch32 configurations are unaffected. Here the ``XN`` bit controls execution
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privileges of the currently executing translation regime, which is the desired
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behaviour.
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- ARM TF EL3 code (for example BL1 and BL31) ensures that all non-secure memory
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mapped into the secure world is non-executable by setting the ``SCR_EL3.SIF``
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bit. See the ``el3_arch_init_common`` macro in ``el3_common_macros.S``.
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.. _CVE-2017-7563: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-7563
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.. _Pull Request #662: https://github.com/ARM-software/arm-trusted-firmware/pull/662
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.. _Pull Request #924: https://github.com/ARM-software/arm-trusted-firmware/pull/924
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